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[209.85.128.178]) by smtp.gmail.com with ESMTPSA id u13-20020a81a50d000000b006047567a828sm384273ywg.96.2024.02.09.09.14.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 09:14:12 -0800 (PST) Received: by mail-yw1-f178.google.com with SMTP id 00721157ae682-6049b115630so15899537b3.1; Fri, 09 Feb 2024 09:14:12 -0800 (PST) X-Received: by 2002:a81:4956:0:b0:604:48a9:44a3 with SMTP id w83-20020a814956000000b0060448a944a3mr1528272ywa.16.1707498851842; Fri, 09 Feb 2024 09:14:11 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> <20240208135045.3728927-2-tudor.ambarus@linaro.org> In-Reply-To: <20240208135045.3728927-2-tudor.ambarus@linaro.org> From: Geert Uytterhoeven Date: Fri, 9 Feb 2024 18:13:59 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property To: Tudor Ambarus Cc: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org, krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Linux-Renesas , Wolfram Sang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Tudor, On Thu, Feb 8, 2024 at 2:51=E2=80=AFPM Tudor Ambarus wrote: > There are instances of the same IP that are configured by the integrator > with different FIFO depths. Introduce the fifo-depth property to allow > such nodes to specify their FIFO depth. > > We haven't seen SPI IPs with different FIFO depths for RX and TX, thus > introduce a single property. Ha... Current documentation for the Clock-Synchronized Serial Interface with FIFO (MSIOF) on e.g. R-Car Gen2 and later states: FIFO capacity: 32 bits =C3=97 64 stages for transmission and 32 bits = =C3=97 256 stages for reception Initially (many years ago), there was some doubt about the validity of these values (older variants on SH supported 64/64), hence drivers/spi/spi-sh-msiof.c still has .tx_fifo_size =3D 64, .rx_fifo_size =3D 64, Probably we should test and revisit this... > --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml > @@ -69,6 +69,11 @@ properties: > Should be generally avoided and be replaced by > spi-cs-high + ACTIVE_HIGH. > > + fifo-depth: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Size of the data FIFO in bytes. I think it is prudent to consider the asymmetric case, too. Whether that should be just two properties ("rx-fifo-depth" and "tx-fifo-depth"), or also a third "fifo-depth", I defer to the DT maintainers... > + > num-cs: > $ref: /schemas/types.yaml#/definitions/uint32 > description: Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds