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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id 3f1490d57ef6-e25e3ef8ef5sm369281276.11.2024.09.27.03.08.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Sep 2024 03:08:04 -0700 (PDT) Received: by mail-yw1-f173.google.com with SMTP id 00721157ae682-6c3f1939d12so17087637b3.2; Fri, 27 Sep 2024 03:08:04 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUk0l+ArMQ4MkZi/4/J8mHLxasMOi4OPulRbl0aAWXBk5WDx0YH7s6fmcRO/XHca6Y2GqJXVlbhXsnUvcpc@vger.kernel.org, AJvYcCWIguPQVw6o2p27fxUQkRwKjZ/pRf8ImQTL3PtjYnmLKdqNzbg0aRyQL37xKyphGITq/zWlbVNmMyZHah1VzO8xqww=@vger.kernel.org, AJvYcCWyepAwCH73ZZ/6xmbaxOBcgcVMbHiTdyQTn9CNRSmReyuw0psnUm8eljZgv0WXwf1aWIvA2WH4ymx2@vger.kernel.org X-Received: by 2002:a05:690c:60c5:b0:6de:1e2:d66a with SMTP id 00721157ae682-6e2474f4adamr19241267b3.2.1727431683946; Fri, 27 Sep 2024 03:08:03 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240926180903.479895-1-sean.anderson@linux.dev> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 27 Sep 2024 12:07:50 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 0/2] arm64: dts: renesas: Add SD/OE pin properties To: Sean Anderson Cc: linux-arm-kernel@lists.infradead.org, Adam Ford , Marian-Cristian Rotariu , Biju Das , Laurent Pinchart , Krzysztof Kozlowski , Rob Herring , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley , Magnus Damm , Geert Uytterhoeven , Olof Johansson , Arnd Bergmann Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Sean, On Thu, Sep 26, 2024 at 8:24=E2=80=AFPM Sean Anderson wrote: > On 9/26/24 14:09, Sean Anderson wrote: > > Linux can configure almost every part of this clock generator without > > relying on the OTP settings. However, the correct configuration for the > > SD/OE pin cannot be determined automatically. Therefore, add the > > appropriate properties to configure this pin. > > > > I have CC'd some people who appear to have access to the following > > boards which use the versaclock5: > > > > - Salvator-X > > - HiHope RZ/G2[MN] Main Board > > - Beacon Embedded Works RZ/G2N Development Kit > > > > as I could not find schematics for these boards. You can help me out by > > (pick one): > > > > - Run the following command and send me the output: > > > > $ grep 10: /sys/kernel/debug/regmap/*-006a/registers On Salvator-X (5p49v5923) and ULCB (5p49v5925): 82 On Salvator-XS (5p49v6901): 8a > > - Inspect (or send me) the schematic to determine the state of the SD/O= E > > pin during normal operation. > > > > My suspicion is that all of these boards use the same configuration > > (SD/OE pin tied high) owing to their common design heritage. Thanks in > > advance. According to the schematics, the SD/OE pin is indeed strapped high on all of the Salvator-X(S), ULCB, HiHope, and Renesom base and SoM boards. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds