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[209.85.222.171]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c7a8951759sm918056885a.31.2025.04.15.07.35.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Apr 2025 07:35:14 -0700 (PDT) Received: by mail-qk1-f171.google.com with SMTP id af79cd13be357-7c542ffec37so569442385a.2; Tue, 15 Apr 2025 07:35:14 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCU6F8p4YPPvlFObdhHsrnGaTNgWGLS2M0bkHynSmUU1cv+7e3xwrpz8EExOq4mS3yB7hz+b1S5C9niotW6j@vger.kernel.org, AJvYcCVhQ3biKLRje57eNcey5sPJ5JE9emHK5GQ7ZgbMwFK4P2HQ9e7n91+7rMR8b7JqMV2vCopfbjuq0DQT@vger.kernel.org, AJvYcCWkShq8Ci4ZDwNb4zrYccHDgV7HzDfAaXNSpu628Rzx4DctNzCYj82UB23TGFrPTb/CQoQLT7CZ4oAy@vger.kernel.org, AJvYcCWzNtdSYzREfg+J9vmsUE0CH0uiAZ5E8nTyYaq6UM6akIOVc/oyf7jzNEVh9JJqIL2nUvbJ8XIB2LDadAKdnOPAS+c=@vger.kernel.org X-Received: by 2002:a05:620a:4492:b0:7c5:5d9b:b626 with SMTP id af79cd13be357-7c7af1f41camr2861018485a.36.1744727714618; Tue, 15 Apr 2025 07:35:14 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 15 Apr 2025 16:35:01 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: ATxdqUHAP61mByLcdD3tXFG3TQoztyO8bwORqwuOtvT7EqjQHrsyUlKYn38EFk8 Message-ID: Subject: Re: [PATCH v2 5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation To: Prabhakar Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" On Mon, 7 Apr 2025 at 18:52, Prabhakar wrote: > From: Lad Prabhakar > > Update the clock enable/disable logic to follow the latest hardware > manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used to > confirm the clock state. > > According to the manual, enabling a clock requires setting the CPG_CLK_ON > bit and verifying the clock has started using the CPG_CLK_MON bit. > Similarly, disabling a clock requires clearing the CPG_CLK_ON bit and > confirming the clock has stopped via the CPG_CLK_MON bit. > > Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then > validate CLK_ON for a more accurate clock status evaluation. > > Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-clk for v6.16. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds