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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id a23-20020a0dd817000000b005a8dbe385d1sm4972779ywe.12.2023.10.25.05.05.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Oct 2023 05:05:00 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id 3f1490d57ef6-d9c687f83a2so5107035276.3; Wed, 25 Oct 2023 05:05:00 -0700 (PDT) X-Received: by 2002:a25:9392:0:b0:d7b:9d44:7574 with SMTP id a18-20020a259392000000b00d7b9d447574mr15722389ybm.64.1698235500116; Wed, 25 Oct 2023 05:05:00 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <46ef748dd27127ef9b39fa6c97fe51e8d3422a4f.1697199949.git.ysato@users.sourceforge.jp> <87ttqf6jjq.wl-ysato@users.sourceforge.jp> In-Reply-To: From: Geert Uytterhoeven Date: Wed, 25 Oct 2023 14:04:48 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU. To: "D. Jeff Dionne" Cc: Yoshinori Sato , linux-sh@vger.kernel.org, glaubitz@physik.fu-berlin.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Jeff, On Wed, Oct 25, 2023 at 1:33=E2=80=AFPM D. Jeff Dionne wrote: > > On Oct 25, 2023, at 20:14, Yoshinori Sato = wrote: > > On Wed, 18 Oct 2023 23:27:43 +0900, > > Geert Uytterhoeven wrote: > >> On Sat, Oct 14, 2023 at 4:54=E2=80=AFPM Yoshinori Sato > >> wrote: > >>> Renesas SuperH binding definition. > >>> > >>> Signed-off-by: Yoshinori Sato > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml > >>> @@ -0,0 +1,45 @@ > >>> +# SPDX-License-Identifier: GPL-2.0 > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: Renesas SuperH CPUs > >>> + > >>> +maintainers: > >>> + - Yoshinori Sato > >>> + > >>> +description: |+ > >>> + The device tree allows to describe the layout of CPUs in a system = through > >>> + the "cpus" node, which in turn contains a number of subnodes (ie "= cpu") > >>> + defining properties for every cpu. > >>> + > >>> + Bindings for CPU nodes follow the Devicetree Specification, availa= ble from: > >>> + > >>> + https://www.devicetree.org/specifications/ > >>> + > >>> +properties: > >>> + compatible: > >>> + items: > >>> + - enum: > >> > >> Missing > >> > >> - jcore,j2 > We must not imply that Renesas is responsible for J2, or that it is a san= ctioned SH core. Compatible values do not declare any such endorsement. > J-Core has the responsibility for maintenance of those SH ISA compatible = cores. The question is: does J2 implement the same instruction set as SH2, i.e. can it run unmodified SH2 code? > >> > >>> + - renesas,sh4 > >> > >> > >>> + - const: renesas,sh > >> > >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to > >> "renesas,sh", though. > >> Is there a common base of instructions that are available on all SH co= res? > > > > The base instruction set is sh2. > > Before that, there is sh1, but this is not compatible with Linux. > > I think it would be a good idea to change this to "renesas,sh2", Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds