[PATCH 0/4] arm64: dts: renesas: Enable I3C on RZ G3S/E

[PATCH 0/4] arm64: dts: renesas: Enable I3C on RZ G3S/E

[Wolfram Sang]

As the dependencies are now upstream (controller driver) or in -next
(clock enablement), the DTS additions to enable the I3C controller on
G3S/E can now be considered for upstream as well.

Patches are on top of renesas-drivers from today. Please let me know
what you think.

Happy hacking,

   Wolfram


Quynh Nguyen (1):
  arm64: dts: renesas: r9a08g045: Add I3C node

Tommaso Merciai (1):
  arm64: dts: renesas: r9a09g047: Add I3C node

Wolfram Sang (2):
  arm64: dts: renesas: rzg3s-smarc-som: Enable I3C
  arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    | 35 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 35 +++++++++++++++++++
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     |  8 +++++
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |  7 ++++
 4 files changed, 85 insertions(+)

-- 
2.47.2

[PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node

[Wolfram Sang]

From: Quynh Nguyen <quynh.nguyen.xb@renesas.com>

Add the I3C node to RZ/G3S SoC DTSI.

Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
[wsa: adapted to upstream driver, moved bus frequencies to board file]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0364f89776e6..6e372e222557 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -272,6 +272,41 @@ channel@8 {
 			};
 		};
 
+		i3c: i3c@1005b000 {
+			compatible = "renesas,r9a08g045-i3c";
+			reg = <0 0x1005b000 0 0x1000>;
+			clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
+				 <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
+			clock-names = "pclk", "tclk";
+			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp", "cmd",
+					  "ibi", "rx", "tx", "rcv","st", "sp",
+					  "tend", "nack", "al", "tmo", "wu", "exit";
+			resets = <&cpg R9A08G045_I3C_PRESETN>,
+				 <&cpg R9A08G045_I3C_TRESETN>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		vbattb: clock-controller@1005c000 {
 			compatible = "renesas,r9a08g045-vbattb";
 			reg = <0 0x1005c000 0 0x1000>;
-- 
2.47.2

[PATCH 2/4] arm64: dts: renesas: r9a09g047: Add I3C node

[Wolfram Sang]

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Add the I3C node to RZ/G3E SoC DTSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764..d2e5f5980185 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -601,6 +601,41 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		i3c0: i3c@12400000 {
+			compatible = "renesas,r9a09g047-i3c";
+			reg = <0 0x12400000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0x91>,
+				 <&cpg CPG_MOD 0x92>,
+				 <&cpg CPG_MOD 0x90>;
+			clock-names = "pclk", "tclk", "pclkrw";
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp",
+					  "cmd", "ibi", "rx", "tx", "rcv",
+					  "st", "sp", "tend", "nack", "al",
+					  "tmo", "wu";
+			resets = <&cpg 0x96>, <&cpg 0x97>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		gpu: gpu@14850000 {
 			compatible = "renesas,r9a09g047-mali",
 				     "arm,mali-bifrost";
-- 
2.47.2

[PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

[Wolfram Sang]

Enable I3C on the dedicated connector of the RZ/G3S module. Provide
safe defaults allowing to connect even to slow I2C devices.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 39845faec894..17fd30df3432 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i3c/i3c.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 #include "rzg3s-smarc-switches.h"
@@ -172,6 +173,12 @@ a0 80 30 30 9c
 	};
 };
 
+&i3c {
+	i2c-scl-hz = <100000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+
 #if SW_CONFIG2 == SW_ON
 /* SD0 slot */
 &sdhi0 {
-- 
2.47.2

[PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

[Wolfram Sang]

Enable I3C on the dedicated connector of the RZ/G3E module. Provide
safe defaults allowing to connect even to slow I2C devices.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 7faa44510d98..0c3156129aae 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -5,6 +5,8 @@
  * Copyright (C) 2024 Renesas Electronics Corp.
  */
 
+#include <dt-bindings/i3c/i3c.h>
+
 /*
  * Please set the below switch position on the SoM and the corresponding macro
  * on the board DTS:
@@ -122,6 +124,12 @@ raa215300: pmic@12 {
 	};
 };
 
+&i3c {
+	i2c-scl-hz = <100000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+
 &mdio0 {
 	phy0: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
-- 
2.47.2

RE: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

[Biju Das]

Hi Wolfram Sang,

Thanks for the patch.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 07 August 2025 16:15
> Subject: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C
> 
> Enable I3C on the dedicated connector of the RZ/G3E module. Provide safe defaults allowing to connect
> even to slow I2C devices.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-
> smarc-som.dtsi
> index 7faa44510d98..0c3156129aae 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -5,6 +5,8 @@
>   * Copyright (C) 2024 Renesas Electronics Corp.
>   */
> 
> +#include <dt-bindings/i3c/i3c.h>
> +
>  /*
>   * Please set the below switch position on the SoM and the corresponding macro
>   * on the board DTS:
> @@ -122,6 +124,12 @@ raa215300: pmic@12 {
>  	};
>  };
> 
> +&i3c {
> +	i2c-scl-hz = <100000>;
> +	i3c-scl-hz = <12500000>;
> +	status = "okay";

What about pinctrl settings here?

Also from the pinctrl xsls sheet there is a note. Have you taken care this?

When the pin function I3C is selected :								
    I3C Bus Interface has a function to switch the pin output to Nch-OpenDrain or CMOS.								
    Use the register on the I3C Bus Interface to switch the pin output mode.								
    At this time, the setting value of PFC_NOD.reg should be 0 (N-ch open drain OFF).

Cheers,
Biju							

Re: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

[wsa+renesas]

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> What about pinctrl settings here?

I overlooked them :( I will let Tommaso handle this because it is not
as trivial as on G3S.


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RE: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

[Biju Das]

Hi Wolfram sang,

> -----Original Message-----
> From: wsa+renesas <wsa+renesas@sang-engineering.com>
> Sent: 07 August 2025 18:00
> Subject: Re: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C
> 
> 
> > What about pinctrl settings here?
> 
> I overlooked them :( I will let Tommaso handle this because it is not as trivial as on G3S.

OK.

Cheers,
Biju

Re: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C

[kernel test robot]

Hi Wolfram,

kernel test robot noticed the following build errors:

[auto build test ERROR on geert-renesas-devel/next]
[also build test ERROR on linus/master next-20250808]
[cannot apply to v6.16]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Wolfram-Sang/arm64-dts-renesas-r9a08g045-Add-I3C-node/20250807-231733
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
patch link:    https://lore.kernel.org/r/20250807151434.5241-10-wsa%2Brenesas%40sang-engineering.com
patch subject: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C
config: arm64-randconfig-001-20250808 (https://download.01.org/0day-ci/archive/20250808/202508082259.wdaPWdYV-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250808/202508082259.wdaPWdYV-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508082259.wdaPWdYV-lkp@intel.com/

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi:127.1-5 Label or path i3c not found
   FATAL ERROR: Syntax error parsing input tree

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node

[Claudiu Beznea]

Hi, Wolfram,

On 07.08.2025 18:14, Wolfram Sang wrote:
> From: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
> 
> Add the I3C node to RZ/G3S SoC DTSI.
> 
> Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
> [wsa: adapted to upstream driver, moved bus frequencies to board file]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 35 ++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> index 0364f89776e6..6e372e222557 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -272,6 +272,41 @@ channel@8 {
>  			};
>  		};
>  
> +		i3c: i3c@1005b000 {
> +			compatible = "renesas,r9a08g045-i3c";
> +			reg = <0 0x1005b000 0 0x1000>;
> +			clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
> +				 <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
> +			clock-names = "pclk", "tclk";
> +			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "ierr", "terr", "abort", "resp", "cmd",
> +					  "ibi", "rx", "tx", "rcv","st", "sp",

Missing a space before "st".

Other than this:
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thank you,
Claudiu

> +					  "tend", "nack", "al", "tmo", "wu", "exit";
> +			resets = <&cpg R9A08G045_I3C_PRESETN>,
> +				 <&cpg R9A08G045_I3C_TRESETN>;
> +			reset-names = "presetn", "tresetn";
> +			power-domains = <&cpg>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		vbattb: clock-controller@1005c000 {
>  			compatible = "renesas,r9a08g045-vbattb";
>  			reg = <0 0x1005c000 0 0x1000>;

Re: [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

[Claudiu Beznea]

Hi, Wolfram,

On 07.08.2025 18:14, Wolfram Sang wrote:
> Enable I3C on the dedicated connector of the RZ/G3S module. Provide
> safe defaults allowing to connect even to slow I2C devices.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> index 39845faec894..17fd30df3432 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -7,6 +7,7 @@
>  
>  #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/i3c/i3c.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>  
>  #include "rzg3s-smarc-switches.h"
> @@ -172,6 +173,12 @@ a0 80 30 30 9c
>  	};
>  };
>  
> +&i3c {
> +	i2c-scl-hz = <100000>;
> +	i3c-scl-hz = <12500000>;

I'm not familiar with I3C but from the HW manual it seems there is some
level of control for I3C in pin controller:
- on Input Enable Control Register (IEN_m) there is this note: Note 1. 1b:
  applies to terminals of TMS_SWDIO, I3C_SCL, I3C_SDA, P1_0, P7_0

- there is I3C_SET register (bit POC) which controls the I3C voltage, so, I
  presume, depending on the SW_I3C_VIO_SEL switch on the board (which
  selects the output of VDD_I3C regulator)  the pins would have to be
  configured with proper power-source = <1800> or power-source = <1200>

Thank you,
Claudiu

> +	status = "okay";
> +};
> +
>  #if SW_CONFIG2 == SW_ON
>  /* SD0 slot */
>  &sdhi0 {

Re: [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C

[Wolfram Sang]

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> - there is I3C_SET register (bit POC) which controls the I3C voltage, so, I
>   presume, depending on the SW_I3C_VIO_SEL switch on the board (which
>   selects the output of VDD_I3C regulator)  the pins would have to be
>   configured with proper power-source = <1800> or power-source = <1200>

I assumed the firmware is setting that bit. Never checked, though, and
can't do before end of August.


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Re: [PATCH 2/4] arm64: dts: renesas: r9a09g047: Add I3C node

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, 7 Aug 2025 at 17:14, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>
> Add the I3C node to RZ/G3E SoC DTSI.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -601,6 +601,41 @@ i2c8: i2c@11c01000 {
>                         status = "disabled";
>                 };
>
> +               i3c0: i3c@12400000 {

Do you want to change this to "i3c", or the "i3c0" in [PATCH 4/4]?
I guess the former, as there is only one instance.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node

[Geert Uytterhoeven]

On Thu, 7 Aug 2025 at 17:14, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
>
> Add the I3C node to RZ/G3S SoC DTSI.
>
> Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
> [wsa: adapted to upstream driver, moved bus frequencies to board file]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -272,6 +272,41 @@ channel@8 {
>                         };
>                 };
>
> +               i3c: i3c@1005b000 {

> +                       interrupt-names = "ierr", "terr", "abort", "resp", "cmd",
> +                                         "ibi", "rx", "tx", "rcv","st", "sp",
> +                                         "tend", "nack", "al", "tmo", "wu", "exit";

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18 with the spacing fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] arm64: dts: renesas: r9a09g047: Add I3C node

[Geert Uytterhoeven]

On Thu, 7 Aug 2025 at 17:14, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>
> Add the I3C node to RZ/G3E SoC DTSI.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -601,6 +601,41 @@ i2c8: i2c@11c01000 {
>                         status = "disabled";
>                 };
>
> +               i3c0: i3c@12400000 {

i3c
Please preserve sort order (by unit address).

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds