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[209.85.219.47]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d3b8f2301asm46168685a.114.2025.06.12.07.37.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jun 2025 07:37:37 -0700 (PDT) Received: by mail-qv1-f47.google.com with SMTP id 6a1803df08f44-6fafb6899c2so12187116d6.0; Thu, 12 Jun 2025 07:37:37 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUIXV+RSf3HCFcINjLhyMLiVXCJp8Utr/spkKjnbSOjtKVFBGhLG9cVwFFJmRzc8RvJc5aCkwVWg0lq@vger.kernel.org, AJvYcCVR1RiL3wmduOLzbLnryOKEJRZ0SvHsLUG5LgFcMgr8ZEAFxea1LuuWQNLgdMIXkwut5HYf4m7rL49a0oNoOlXqt90=@vger.kernel.org, AJvYcCX3VTijhjGNS8Jo/prSLGrrGkdmVbRUrwUwd7lDwB5nhQGz0vBQosqBgYgwYFAh5R6pV87nOjQ/Ab8S5hzO@vger.kernel.org, AJvYcCXRyR9/mOzEAitOO6L22CSvoa+mwD4xFeQZu8BPpqq1ARW0iPK6m9CgxAhyL4M6whe7cPB/JBvDEKON@vger.kernel.org X-Received: by 2002:a05:6214:202e:b0:6fa:f59f:f349 with SMTP id 6a1803df08f44-6fb347f3f5fmr56720356d6.10.1749739057314; Thu, 12 Jun 2025 07:37:37 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250609203656.333138-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250609203656.333138-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 12 Jun 2025 16:37:25 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AX0GCFsuq2UTCzvbMhu6t2eErAlrMWnHmknmauMa46mODIPLG40ClLlm4kMFDTw Message-ID: Subject: Re: [PATCH 5/8] arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC To: Prabhakar Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Prabhakar Content-Type: text/plain; charset="UTF-8" Hi Prabhakar, On Mon, 9 Jun 2025 at 22:37, Prabhakar wrote: > From: Lad Prabhakar > > Add initial SoC DTSI for Renesas RZ/N2H ("R9A09G087") SoC, below are > the list of blocks added: > - EXT CLKs > - 4X CA55 > - SCIF > - CPG > - GIC > - ARMv8 Timer > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi > @@ -0,0 +1,135 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/N2H SoC > + * > + * Copyright (C) 2025 Renesas Electronics Corp. > + */ > + > +#define RZN2H_PINS_PER_PORT 8 > + > +/* > + * Create the pin index from its bank and position numbers and store in > + * the upper 16 bits the alternate function identifier > + */ > +#define RZN2H_PORT_PINMUX(b, p, f) ((b) * RZN2H_PINS_PER_PORT + (p) | ((f) << 16)) > + > +/* Convert a port and pin label to its global pin index */ > +#define RZN2H_GPIO(port, pin) ((port) * RZN2H_PINS_PER_PORT + (pin)) These 3 defines belong in the (future) patch that adds the pinctrl node. > + timer { > + compatible = "arm,armv8-timer"; > + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, > + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; Thanks, this brought to my attention that the node in the posted RZ/T2H patch is wrong ;-) > + }; > +}; The rest LGTM, so with the above fixed: Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds