From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v2 1/5] clk: renesas: r9a09g077: Propagate rate changes to parent clocks
Date: Mon, 10 Nov 2025 14:18:06 +0100 [thread overview]
Message-ID: <CAMuHMdVAyN-XQVoBNncCC5Jka4TMqSeswe8frht9sPOEJB+VLw@mail.gmail.com> (raw)
In-Reply-To: <20251028165127.991351-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Tue, 28 Oct 2025 at 17:51, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the CLK_SET_RATE_PARENT flag to divider clock registration so that rate
> changes can propagate to parent clocks when needed. This allows the CPG
> divider clocks to request rate adjustments from their parent, ensuring
> correct frequency scaling and improved flexibility in clock rate selection.
>
> Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2025-11-10 13:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 16:51 [PATCH v2 0/5] Add XSPI clocks and improve divider clock handling for R9A09G077 SoC Prabhakar
2025-10-28 16:51 ` [PATCH v2 1/5] clk: renesas: r9a09g077: Propagate rate changes to parent clocks Prabhakar
2025-11-10 13:18 ` Geert Uytterhoeven [this message]
2025-10-28 16:51 ` [PATCH v2 2/5] clk: renesas: r9a09g077: Remove stray blank line Prabhakar
2025-11-10 13:18 ` Geert Uytterhoeven
2025-10-28 16:51 ` [PATCH v2 3/5] clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration Prabhakar
2025-11-10 13:19 ` Geert Uytterhoeven
2025-10-28 16:51 ` [PATCH v2 4/5] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Prabhakar
2025-10-28 16:51 ` [PATCH v2 5/5] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar
2025-11-10 13:48 ` Geert Uytterhoeven
2025-11-10 21:38 ` Lad, Prabhakar
2025-11-17 10:52 ` Lad, Prabhakar
2025-11-17 13:28 ` Geert Uytterhoeven
2025-11-17 20:25 ` Lad, Prabhakar
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