* [PATCH v2 0/5] Add support for the RZ/V2H Interrupt Control Unit
@ 2024-09-30 14:52 Fabrizio Castro
2024-09-30 14:52 ` [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Fabrizio Castro
2024-09-30 14:52 ` [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node Fabrizio Castro
0 siblings, 2 replies; 7+ messages in thread
From: Fabrizio Castro @ 2024-09-30 14:52 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Turquette, Stephen Boyd, Linus Walleij, Philipp Zabel,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, linux-kernel, devicetree,
linux-renesas-soc, linux-clk, linux-gpio, Chris Paterson,
Biju Das, Lad Prabhakar
Dear All,
This series adds whatever is required for supporting NMI, IRQ, and
TINT interrupts to the Renesas RZ/V2H SoC.
v1->v2:
* Dropped patch "dt-bindings: pinctrl: renesas: rzg2l-pinctrl: Add interrupt-parent".
* Patch "dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller"
amended as per Rob's comments.
* Patch "irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver"
fixed missing put_device.
Thanks,
Fab
Fabrizio Castro (5):
pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX
dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt
Controller
clk: renesas: r9a09g057: Add clock and reset entries for ICU
irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver
arm64: dts: renesas: r9a09g057: Add ICU node
.../renesas,rzv2h-icu.yaml | 276 +++++++++
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 88 +++
drivers/clk/renesas/r9a09g057-cpg.c | 2 +
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-rzv2h.c | 527 ++++++++++++++++++
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +-
drivers/soc/renesas/Kconfig | 1 +
8 files changed, 908 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
create mode 100644 drivers/irqchip/irq-renesas-rzv2h.c
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller 2024-09-30 14:52 [PATCH v2 0/5] Add support for the RZ/V2H Interrupt Control Unit Fabrizio Castro @ 2024-09-30 14:52 ` Fabrizio Castro 2024-10-02 20:22 ` Rob Herring (Arm) 2024-10-04 10:26 ` Geert Uytterhoeven 2024-09-30 14:52 ` [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node Fabrizio Castro 1 sibling, 2 replies; 7+ messages in thread From: Fabrizio Castro @ 2024-09-30 14:52 UTC (permalink / raw) To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven Cc: Fabrizio Castro, Magnus Damm, linux-kernel, devicetree, linux-renesas-soc, Chris Paterson, Biju Das, Lad Prabhakar Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. Also add macros for the NMI and IRQ0-15 interrupts which map the SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be used in the first cell of the interrupt specifiers. For the second cell of the interrupt specifier, since NMI, IRQn and TINTn support different types of interrupts between themselves, add helper macros to make it easier for the user to work out what's available. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- v1->v2: * Removed '|' from main description * Reworked main description * Fixed indentation of #interrupt-cells * Reworked description of #interrupt-cells * Dropped file include/dt-bindings/interrupt-controller/icu-rzv2h.h .../renesas,rzv2h-icu.yaml | 276 ++++++++++++++++++ 1 file changed, 276 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml new file mode 100644 index 000000000000..3c48e9c2a954 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Interrupt Control Unit + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +description: + The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, and + TINT), error interrupts, DMAC requests, GPT interrupts, and internal + interrupts. + +properties: + compatible: + const: renesas,r9a09g057-icu # RZ/V2H(P) + + '#interrupt-cells': + description: The first cell is the SPI number of the NMI or the + PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to + specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + minItems: 58 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: IRQ8 interrupt + - description: IRQ9 interrupt + - description: IRQ10 interrupt + - description: IRQ11 interrupt + - description: IRQ12 interrupt + - description: IRQ13 interrupt + - description: IRQ14 interrupt + - description: IRQ15 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Software interrupt, INTA55_0 + - description: Software interrupt, INTA55_1 + - description: Software interrupt, INTA55_2 + - description: Software interrupt, INTA55_3 + - description: Error interrupt to CA55 + - description: GTCCRA compare match/input capture (U0) + - description: GTCCRB compare match/input capture (U0) + - description: GTCCRA compare match/input capture (U1) + - description: GTCCRB compare match/input capture (U1) + + interrupt-names: + minItems: 58 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: irq8 + - const: irq9 + - const: irq10 + - const: irq11 + - const: irq12 + - const: irq13 + - const: irq14 + - const: irq15 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: int-ca55-0 + - const: int-ca55-1 + - const: int-ca55-2 + - const: int-ca55-3 + - const: icu-error-ca55 + - const: gpt-u0-gtciada + - const: gpt-u0-gtciadb + - const: gpt-u1-gtciada + - const: gpt-u1-gtciadb + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/renesas-cpg-mssr.h> + + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g057-icu"; + reg = <0x10400000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller 2024-09-30 14:52 ` [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Fabrizio Castro @ 2024-10-02 20:22 ` Rob Herring (Arm) 2024-10-04 10:26 ` Geert Uytterhoeven 1 sibling, 0 replies; 7+ messages in thread From: Rob Herring (Arm) @ 2024-10-02 20:22 UTC (permalink / raw) To: Fabrizio Castro Cc: Lad Prabhakar, Biju Das, devicetree, linux-renesas-soc, Thomas Gleixner, Conor Dooley, Magnus Damm, linux-kernel, Chris Paterson, Geert Uytterhoeven, Krzysztof Kozlowski On Mon, 30 Sep 2024 15:52:41 +0100, Fabrizio Castro wrote: > Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. > > Also add macros for the NMI and IRQ0-15 interrupts which map the > SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be > used in the first cell of the interrupt specifiers. > > For the second cell of the interrupt specifier, since NMI, IRQn > and TINTn support different types of interrupts between themselves, > add helper macros to make it easier for the user to work out what's > available. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > v1->v2: > * Removed '|' from main description > * Reworked main description > * Fixed indentation of #interrupt-cells > * Reworked description of #interrupt-cells > * Dropped file include/dt-bindings/interrupt-controller/icu-rzv2h.h > > .../renesas,rzv2h-icu.yaml | 276 ++++++++++++++++++ > 1 file changed, 276 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller 2024-09-30 14:52 ` [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Fabrizio Castro 2024-10-02 20:22 ` Rob Herring (Arm) @ 2024-10-04 10:26 ` Geert Uytterhoeven 2024-10-09 22:10 ` Fabrizio Castro 1 sibling, 1 reply; 7+ messages in thread From: Geert Uytterhoeven @ 2024-10-04 10:26 UTC (permalink / raw) To: Fabrizio Castro Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-kernel, devicetree, linux-renesas-soc, Chris Paterson, Biju Das, Lad Prabhakar Hi Fabrizio, On Mon, Sep 30, 2024 at 4:53 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. > > Also add macros for the NMI and IRQ0-15 interrupts which map the > SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be > used in the first cell of the interrupt specifiers. > > For the second cell of the interrupt specifier, since NMI, IRQn > and TINTn support different types of interrupts between themselves, > add helper macros to make it easier for the user to work out what's > available. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > v1->v2: > * Removed '|' from main description > * Reworked main description > * Fixed indentation of #interrupt-cells > * Reworked description of #interrupt-cells > * Dropped file include/dt-bindings/interrupt-controller/icu-rzv2h.h Thanks for the update! > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml > +properties: > + compatible: > + const: renesas,r9a09g057-icu # RZ/V2H(P) Too many spaces before "#"? > + > + '#interrupt-cells': > + description: The first cell is the SPI number of the NMI or the > + PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to > + specify the flag. > + const: 2 > + > + '#address-cells': > + const: 0 > + > + interrupt-controller: true > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 58 > + items: > + - description: NMI interrupt > + - description: IRQ0 interrupt > + - description: IRQ1 interrupt > + - description: IRQ2 interrupt > + - description: IRQ3 interrupt > + - description: IRQ4 interrupt > + - description: IRQ5 interrupt > + - description: IRQ6 interrupt > + - description: IRQ7 interrupt > + - description: IRQ8 interrupt > + - description: IRQ9 interrupt > + - description: IRQ10 interrupt > + - description: IRQ11 interrupt > + - description: IRQ12 interrupt > + - description: IRQ13 interrupt > + - description: IRQ14 interrupt > + - description: IRQ15 interrupt "PORT_IRQ<n>", to match Table 4.6-22 ("List of Input Events") and '#interrupt-cells' above. > + - description: GPIO interrupt, TINT0 > + - description: GPIO interrupt, TINT1 > + - description: GPIO interrupt, TINT2 > + - description: GPIO interrupt, TINT3 > + - description: GPIO interrupt, TINT4 > + - description: GPIO interrupt, TINT5 > + - description: GPIO interrupt, TINT6 > + - description: GPIO interrupt, TINT7 > + - description: GPIO interrupt, TINT8 > + - description: GPIO interrupt, TINT9 > + - description: GPIO interrupt, TINT10 > + - description: GPIO interrupt, TINT11 > + - description: GPIO interrupt, TINT12 > + - description: GPIO interrupt, TINT13 > + - description: GPIO interrupt, TINT14 > + - description: GPIO interrupt, TINT15 > + - description: GPIO interrupt, TINT16 > + - description: GPIO interrupt, TINT17 > + - description: GPIO interrupt, TINT18 > + - description: GPIO interrupt, TINT19 > + - description: GPIO interrupt, TINT20 > + - description: GPIO interrupt, TINT21 > + - description: GPIO interrupt, TINT22 > + - description: GPIO interrupt, TINT23 > + - description: GPIO interrupt, TINT24 > + - description: GPIO interrupt, TINT25 > + - description: GPIO interrupt, TINT26 > + - description: GPIO interrupt, TINT27 > + - description: GPIO interrupt, TINT28 > + - description: GPIO interrupt, TINT29 > + - description: GPIO interrupt, TINT30 > + - description: GPIO interrupt, TINT31 > + - description: Software interrupt, INTA55_0 > + - description: Software interrupt, INTA55_1 > + - description: Software interrupt, INTA55_2 > + - description: Software interrupt, INTA55_3 > + - description: Error interrupt to CA55 > + - description: GTCCRA compare match/input capture (U0) > + - description: GTCCRB compare match/input capture (U0) > + - description: GTCCRA compare match/input capture (U1) > + - description: GTCCRB compare match/input capture (U1) > + > + interrupt-names: > + minItems: 58 > + items: > + - const: nmi > + - const: irq0 > + - const: irq1 > + - const: irq2 > + - const: irq3 > + - const: irq4 > + - const: irq5 > + - const: irq6 > + - const: irq7 > + - const: irq8 > + - const: irq9 > + - const: irq10 > + - const: irq11 > + - const: irq12 > + - const: irq13 > + - const: irq14 > + - const: irq15 port_irq<n>? The rest LGTM, although I think you may want to add more interrupts later, for various events? However, it's not really clear to me which interrupts go through the ICU, and which go directly to the GIC. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller 2024-10-04 10:26 ` Geert Uytterhoeven @ 2024-10-09 22:10 ` Fabrizio Castro 0 siblings, 0 replies; 7+ messages in thread From: Fabrizio Castro @ 2024-10-09 22:10 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson, Biju Das, Prabhakar Mahadev Lad Hi Geert, Thanks for your feedback! > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: Friday, October 4, 2024 11:26 AM > Subject: Re: [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt > Controller > > Hi Fabrizio, > > On Mon, Sep 30, 2024 at 4:53 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > > Add DT bindings for the Renesas RZ/V2H(P) Interrupt Controller. > > > > Also add macros for the NMI and IRQ0-15 interrupts which map the > > SPI0-16 interrupts on the RZ/V2H(P) SoC so that they can be used in > > the first cell of the interrupt specifiers. > > > > For the second cell of the interrupt specifier, since NMI, IRQn and > > TINTn support different types of interrupts between themselves, add > > helper macros to make it easier for the user to work out what's > > available. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > --- > > v1->v2: > > * Removed '|' from main description > > * Reworked main description > > * Fixed indentation of #interrupt-cells > > * Reworked description of #interrupt-cells > > * Dropped file include/dt-bindings/interrupt-controller/icu-rzv2h.h > > Thanks for the update! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r > > +++ zv2h-icu.yaml > > > +properties: > > + compatible: > > + const: renesas,r9a09g057-icu # RZ/V2H(P) > > Too many spaces before "#"? Indeed. I'll replace with 1 space. > > > + > > + '#interrupt-cells': > > + description: The first cell is the SPI number of the NMI or the > > + PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to > > + specify the flag. > > + const: 2 > > + > > + '#address-cells': > > + const: 0 > > + > > + interrupt-controller: true > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + minItems: 58 > > + items: > > + - description: NMI interrupt > > + - description: IRQ0 interrupt > > + - description: IRQ1 interrupt > > + - description: IRQ2 interrupt > > + - description: IRQ3 interrupt > > + - description: IRQ4 interrupt > > + - description: IRQ5 interrupt > > + - description: IRQ6 interrupt > > + - description: IRQ7 interrupt > > + - description: IRQ8 interrupt > > + - description: IRQ9 interrupt > > + - description: IRQ10 interrupt > > + - description: IRQ11 interrupt > > + - description: IRQ12 interrupt > > + - description: IRQ13 interrupt > > + - description: IRQ14 interrupt > > + - description: IRQ15 interrupt > > "PORT_IRQ<n>", to match Table 4.6-22 ("List of Input Events") and '#interrupt-cells' above. Good shout. > > > + - description: GPIO interrupt, TINT0 > > + - description: GPIO interrupt, TINT1 > > + - description: GPIO interrupt, TINT2 > > + - description: GPIO interrupt, TINT3 > > + - description: GPIO interrupt, TINT4 > > + - description: GPIO interrupt, TINT5 > > + - description: GPIO interrupt, TINT6 > > + - description: GPIO interrupt, TINT7 > > + - description: GPIO interrupt, TINT8 > > + - description: GPIO interrupt, TINT9 > > + - description: GPIO interrupt, TINT10 > > + - description: GPIO interrupt, TINT11 > > + - description: GPIO interrupt, TINT12 > > + - description: GPIO interrupt, TINT13 > > + - description: GPIO interrupt, TINT14 > > + - description: GPIO interrupt, TINT15 > > + - description: GPIO interrupt, TINT16 > > + - description: GPIO interrupt, TINT17 > > + - description: GPIO interrupt, TINT18 > > + - description: GPIO interrupt, TINT19 > > + - description: GPIO interrupt, TINT20 > > + - description: GPIO interrupt, TINT21 > > + - description: GPIO interrupt, TINT22 > > + - description: GPIO interrupt, TINT23 > > + - description: GPIO interrupt, TINT24 > > + - description: GPIO interrupt, TINT25 > > + - description: GPIO interrupt, TINT26 > > + - description: GPIO interrupt, TINT27 > > + - description: GPIO interrupt, TINT28 > > + - description: GPIO interrupt, TINT29 > > + - description: GPIO interrupt, TINT30 > > + - description: GPIO interrupt, TINT31 > > + - description: Software interrupt, INTA55_0 > > + - description: Software interrupt, INTA55_1 > > + - description: Software interrupt, INTA55_2 > > + - description: Software interrupt, INTA55_3 > > + - description: Error interrupt to CA55 > > + - description: GTCCRA compare match/input capture (U0) > > + - description: GTCCRB compare match/input capture (U0) > > + - description: GTCCRA compare match/input capture (U1) > > + - description: GTCCRB compare match/input capture (U1) > > + > > + interrupt-names: > > + minItems: 58 > > + items: > > + - const: nmi > > + - const: irq0 > > + - const: irq1 > > + - const: irq2 > > + - const: irq3 > > + - const: irq4 > > + - const: irq5 > > + - const: irq6 > > + - const: irq7 > > + - const: irq8 > > + - const: irq9 > > + - const: irq10 > > + - const: irq11 > > + - const: irq12 > > + - const: irq13 > > + - const: irq14 > > + - const: irq15 > > port_irq<n>? Will change. > > The rest LGTM, although I think you may want to add more interrupts later, for various events? However, > it's not really clear to me which interrupts go through the ICU, and which go directly to the GIC. The interrupts listed in here are the ones from Table 4.6-23 where ICU is explicitly listed in the "Unit" column, on top of the interrupts coming from PFC. We'll add more interrupts if needed later on, because as you said, some things are not super clear from the manual. I'll send a new version soon. Kind regards, Fab > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But when I'm talking to > journalists I just say "programmer" or something like that. > -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node 2024-09-30 14:52 [PATCH v2 0/5] Add support for the RZ/V2H Interrupt Control Unit Fabrizio Castro 2024-09-30 14:52 ` [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Fabrizio Castro @ 2024-09-30 14:52 ` Fabrizio Castro 2024-10-04 10:27 ` Geert Uytterhoeven 1 sibling, 1 reply; 7+ messages in thread From: Fabrizio Castro @ 2024-09-30 14:52 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven Cc: Fabrizio Castro, Magnus Damm, linux-renesas-soc, devicetree, linux-kernel, Chris Paterson, Biju Das, Lad Prabhakar Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2H(P) SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- v1->v2: * No change arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1ad5a1b6917f..72d54aa68e37 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -90,6 +90,93 @@ soc: soc { #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g057-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g057-pinctrl"; reg = <0 0x10410000 0 0x10000>; @@ -99,6 +186,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges = <&pinctrl 0 0 96>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node 2024-09-30 14:52 ` [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node Fabrizio Castro @ 2024-10-04 10:27 ` Geert Uytterhoeven 0 siblings, 0 replies; 7+ messages in thread From: Geert Uytterhoeven @ 2024-10-04 10:27 UTC (permalink / raw) To: Fabrizio Castro Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm, linux-renesas-soc, devicetree, linux-kernel, Chris Paterson, Biju Das, Lad Prabhakar On Mon, Sep 30, 2024 at 4:53 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > Add node for the Interrupt Control Unit IP found on the Renesas > RZ/V2H(P) SoC, and modify the pinctrl node as its interrupt parent > is the ICU node. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > v1->v2: > * No change Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-10-09 22:10 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-09-30 14:52 [PATCH v2 0/5] Add support for the RZ/V2H Interrupt Control Unit Fabrizio Castro 2024-09-30 14:52 ` [PATCH v2 2/5] dt-bindings: interrupt-controller: Add Renesas RZ/V2H(P) Interrupt Controller Fabrizio Castro 2024-10-02 20:22 ` Rob Herring (Arm) 2024-10-04 10:26 ` Geert Uytterhoeven 2024-10-09 22:10 ` Fabrizio Castro 2024-09-30 14:52 ` [PATCH v2 5/5] arm64: dts: renesas: r9a09g057: Add ICU node Fabrizio Castro 2024-10-04 10:27 ` Geert Uytterhoeven
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).