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[209.85.217.51]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-4e7e70c6886sm1534977137.24.2025.06.17.00.16.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Jun 2025 00:16:56 -0700 (PDT) Received: by mail-vs1-f51.google.com with SMTP id ada2fe7eead31-4e77d1333aeso1460299137.0; Tue, 17 Jun 2025 00:16:55 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUS+77P2SATXhNdpDT94nv+r1Gnx7XVmyhm2c+B9v3DjTBm08wAER9lbcuWwNaCPK5+Cr1BBIZeAaqH@vger.kernel.org, AJvYcCUiiXCZXAa5vB0GXCJ+5EjVJG5GXS5E6ZtR4LT7oAAXUC7KOEgD7dV0/qDf8COUtRzLKL3B5gA7H/MH@vger.kernel.org, AJvYcCWOWdRDQoIHejzUeV1KXMHKHkXy2uuo6NergREDwmi9cnIVc32At5lqFNSJkcimuWvaqEu8wQLNiua0Ts45EXTrUAY=@vger.kernel.org, AJvYcCWwHSGBXry1Imvudr4WDmYlc8zvAa1wQEBgksnoejgvZr2FGANQmyr7ikQQhjT7XcMi5kQDlgF99D83Zhnt@vger.kernel.org X-Received: by 2002:a05:6102:4a98:b0:4e6:a338:a421 with SMTP id ada2fe7eead31-4e7f61b1f1bmr7111790137.6.1750144615617; Tue, 17 Jun 2025 00:16:55 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 17 Jun 2025 09:16:43 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AX0GCFvTdSEkTtmnY7ITCikl3hKxLbzpvQWPX_2lfUXVw80Wv9KR5OXOX2w3SaQ Message-ID: Subject: Re: [PATCH 3/8] dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support To: "Lad, Prabhakar" Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Prabhakar, On Fri, 13 Jun 2025 at 17:29, Lad, Prabhakar w= rote: > On Thu, Jun 12, 2025 at 3:38=E2=80=AFPM Geert Uytterhoeven wrote: > > On Mon, 9 Jun 2025 at 22:37, Prabhakar wro= te: > > > From: Lad Prabhakar > > > > > > Document support for Module Standby and Software Reset found on the > > > > the Clock Generator and Module Standby and Software Reset > > > Ok, I'll amend the commit message as above. > > > > Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset= IP > > > > Clock Generator and ... > > > Ok, I'll amend the commit message as above. > > > > is similar to that found on the RZ/T2H SoC. > > > > > > Signed-off-by: Lad Prabhakar > > > > > --- /dev/null > > > +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h > > > @@ -0,0 +1,28 @@ > > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > + * > > > + * Copyright (C) 2025 Renesas Electronics Corp. > > > + */ > > > + > > > +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ > > > +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ > > > + > > > +#include > > > + > > > +/* R9A09G087 CPG Core Clocks */ > > > +#define R9A09G087_CLK_CA55C0 0 > > > +#define R9A09G087_CLK_CA55C1 1 > > > +#define R9A09G087_CLK_CA55C2 2 > > > +#define R9A09G087_CLK_CA55C3 3 > > > +#define R9A09G087_CLK_CA55S 4 > > > +#define R9A09G087_CLK_CR52_CPU0 5 > > > +#define R9A09G087_CLK_CR52_CPU1 6 > > > +#define R9A09G087_CLK_CKIO 7 > > > +#define R9A09G087_CLK_PCLKAH 8 > > > +#define R9A09G087_CLK_PCLKAM 9 > > > +#define R9A09G087_CLK_PCLKAL 10 > > > +#define R9A09G087_CLK_PCLKGPTL 11 > > > +#define R9A09G087_CLK_PCLKH 12 > > > +#define R9A09G087_CLK_PCLKM 13 > > > +#define R9A09G087_CLK_PCLKL 14 > > > > The RZ/T2H DT bindings file lacks PCLKL, which was probably a harmless > > oversight (it can always be added later), as it does exist on RZ/T2H, > > too, according to the documentation. > > > > However, given drivers/clk/renesas/r9a09g077-cpg.c has > > LAST_DT_CORE_CLK =3D R9A09G077_CLK_PCLKM, > > using R9A09G087_CLK_PCLKL will lead to wrong results. > > > > So either you want to add R9A09G077_CLK_PCLKL and update > > LAST_DT_CORE_CLK first, or set LAST_DT_CORE_CLK to R9A09G087_CLK_PCLKL > > in this patch. > > > Actually I already have a patch which includes a couple of fixes and > to the orignal bring up series for T2H + I2C support which adds > R9A09G077_CLK_PCLKL and updates LAST_DT_CORE_CLK. I intend to send > them when the base patches are accepted. As there are no users for > PCLKL in the bringup series this won't cause any issues. Is that OK > with you? Please include that fix in your v2 series, to avoid any possible issues with using R9A09G087_CLK_PCLKL. Thanks! Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds