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[209.85.217.51]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53936b169ffsm4080042e0c.6.2025.08.06.02.11.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 02:11:37 -0700 (PDT) Received: by mail-vs1-f51.google.com with SMTP id ada2fe7eead31-5006f7e71aeso1246167137.1; Wed, 06 Aug 2025 02:11:37 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVCA6yEjir4ASJRnBmiANU04pkxbMAuUl98n3VYgqSU3UMf3qDUtP8ECS/Iz29KEkeJwK/7CL+M3MAciGBw@vger.kernel.org, AJvYcCVq5bMk2x8B1/qeFbtTdnafCDl5iDdPdvrO+SGHIrRVIR9CuduSEGBEqmBQ1M/WQZy3SP3ZZXFUsPkv@vger.kernel.org, AJvYcCXj9EHciU2RjXDpM3enAYlijW3+/1+AdOsiQOZQLZZomiGAArKy4b5kAMyXb+fuQAv9YuLkppFASqYF45drWzzzOk0=@vger.kernel.org X-Received: by 2002:a05:6102:e13:b0:4e6:d784:3f7 with SMTP id ada2fe7eead31-5037aae01f0mr648606137.15.1754471497092; Wed, 06 Aug 2025 02:11:37 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250629220502.935717-1-marek.vasut+renesas@mailbox.org> In-Reply-To: <20250629220502.935717-1-marek.vasut+renesas@mailbox.org> From: Geert Uytterhoeven Date: Wed, 6 Aug 2025 11:11:26 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXyTLkQ8Fim5zNUDUaYka6FZ4b931A7kHxZ4txshhqX1WT490uS4CUxX-bc Message-ID: Subject: Re: [PATCH] ARM: dts: renesas: Add boot phase tags marking to Renesas RZ/A1 To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , Krzysztof Kozlowski , Magnus Damm , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Hi Marek, On Mon, 30 Jun 2025 at 00:05, Marek Vasut wrote: > bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) > to describe various node usage during boot phases with DT. Add bootph-all for > all nodes that are used in the bootloader on Renesas RZ/A1 SoC. > > All SoC require BSC bus, PFC pin control and OSTM0 timer access during all > stages of the boot process, those are marked using bootph-all property, and > so is the SoC bus node which contains the PFC and OSTM IPs. > > Each board console UART is also marked as bootph-all to make it available in > all stages of the boot process. > > Signed-off-by: Marek Vasut Thanks for your patch! > --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi > +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi > @@ -41,6 +41,7 @@ bsc: bus { > #address-cells = <1>; > #size-cells = <1>; > ranges = <0 0 0x18000000>; > + bootph-all; > }; > > cpus { > @@ -108,6 +109,8 @@ soc { > #size-cells = <1>; > ranges; > Please drop this blank line. > + bootph-all; > + > L2: cache-controller@3ffff000 { > compatible = "arm,pl310-cache"; > reg = <0x3ffff000 0x1000>; > @@ -639,6 +643,7 @@ ostm0: timer@fcfec000 { > interrupts = ; > clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; > power-domains = <&cpg_clocks>; > + bootph-all; Please move this to the board-specific .dts files, where this node is enabled. > status = "disabled"; > }; > Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds