From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 References: <1549528310-54436-1-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1549528310-54436-1-git-send-email-biju.das@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 7 Feb 2019 11:13:03 +0100 Message-ID: Subject: Re: [PATCH 1/2] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Content-Type: text/plain; charset="UTF-8" To: Biju Das Cc: Rob Herring , Mark Rutland , Simon Horman , Magnus Damm , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Chris Paterson , Fabrizio Castro List-ID: On Thu, Feb 7, 2019 at 9:37 AM Biju Das wrote: > Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges > mapping for pciec0 node. Also declare pcie bus clock, since it is > generated on the CAT874 main board. > > Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds