* [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H [not found] <20250519215734.577053-1-thierry.bultel.yh@bp.renesas.com> @ 2025-05-19 21:57 ` Thierry Bultel 2025-05-26 17:02 ` Geert Uytterhoeven 2025-05-19 21:57 ` [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC Thierry Bultel 1 sibling, 1 reply; 6+ messages in thread From: Thierry Bultel @ 2025-05-19 21:57 UTC (permalink / raw) To: thierry.bultel Cc: linux-renesas-soc, geert, paul.barker.ct, Thierry Bultel, Geert Uytterhoeven, linux-gpio, devicetree, linux-kernel Document RZ/T2H (a.k.a r9a09g077) pinctrl Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> --- .../bindings/pinctrl/renesas,pfc.yaml | 59 +++++++++++++------ include/dt-bindings/pinctrl/rzt2h-pinctrl.h | 23 ++++++++ 2 files changed, 65 insertions(+), 17 deletions(-) create mode 100644 include/dt-bindings/pinctrl/rzt2h-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index cfe004573366..6d6f97daad17 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -29,6 +29,7 @@ properties: - renesas,pfc-r8a774b1 # RZ/G2N - renesas,pfc-r8a774c0 # RZ/G2E - renesas,pfc-r8a774e1 # RZ/G2H + - renesas,pfc-r9a09g077 # RZ/T2H - renesas,pfc-r8a7778 # R-Car M1 - renesas,pfc-r8a7779 # R-Car H1 - renesas,pfc-r8a7790 # R-Car H2 @@ -74,27 +75,41 @@ properties: power-domains: maxItems: 1 -allOf: - - $ref: pinctrl.yaml# - required: - compatible - reg -if: - properties: - compatible: - enum: - - renesas,pfc-r8a73a4 - - renesas,pfc-r8a7740 - - renesas,pfc-sh73a0 -then: - required: - - interrupts-extended - - gpio-controller - - '#gpio-cells' - - gpio-ranges - - power-domains +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + enum: + - renesas,pfc-r8a73a4 + - renesas,pfc-r8a7740 + - renesas,pfc-sh73a0 + then: + required: + - interrupts-extended + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - power-domains + - if: + properties: + compatible: + contains: + const: renesas,pfc-r9a09g077 + then: + required: + - gpio-controller + - '#gpio-cells' + - gpio-ranges + properties: + reg: + items: + - description: base address of register block 0 + - description: base address of register block 1 additionalProperties: anyOf: @@ -194,3 +209,13 @@ examples: power-source = <3300>; }; }; + + - | + pinctrl: pinctrl@812c0000 { + compatible = "renesas,pfc-r9a09g077"; + reg = <0x802c0000 0x2000>, + <0x812c0000 0x2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 287>; + }; diff --git a/include/dt-bindings/pinctrl/rzt2h-pinctrl.h b/include/dt-bindings/pinctrl/rzt2h-pinctrl.h new file mode 100644 index 000000000000..7842783fdb7a --- /dev/null +++ b/include/dt-bindings/pinctrl/rzt2h-pinctrl.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/T2H family pinctrl bindings. + * + * Copyright (C) 2025 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_RZT2H_PINCTRL_H +#define __DT_BINDINGS_RZT2H_PINCTRL_H + +#define RZT2H_PINS_PER_PORT 8 + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16)) + +/* Convert a port and pin label to its global pin index */ +#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_RZT2H_PINCTRL_H */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H 2025-05-19 21:57 ` [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H Thierry Bultel @ 2025-05-26 17:02 ` Geert Uytterhoeven 2025-06-02 7:11 ` Lad, Prabhakar 0 siblings, 1 reply; 6+ messages in thread From: Geert Uytterhoeven @ 2025-05-26 17:02 UTC (permalink / raw) To: Thierry Bultel Cc: thierry.bultel, linux-renesas-soc, paul.barker.ct, linux-gpio, devicetree, linux-kernel Hi Thierry, On Mon, 19 May 2025 at 23:57, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote: > Document RZ/T2H (a.k.a r9a09g077) pinctrl > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Thanks for your patch! > --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > @@ -29,6 +29,7 @@ properties: > - renesas,pfc-r8a774b1 # RZ/G2N > - renesas,pfc-r8a774c0 # RZ/G2E > - renesas,pfc-r8a774e1 # RZ/G2H > + - renesas,pfc-r9a09g077 # RZ/T2H > - renesas,pfc-r8a7778 # R-Car M1 > - renesas,pfc-r8a7779 # R-Car H1 > - renesas,pfc-r8a7790 # R-Car H2 From a quick glance at the docs and driver, adding support for RZ/T2H to this DT binding is a not good match, as the RZ/T2H PFC hardware does not have the concept of pin groups and functions. Using separate DT bindings, as for most other SoCs in the RZ family, also allows you to use the preferred order "renesas,r9a09g077-<foo>". > @@ -194,3 +209,13 @@ examples: > power-source = <3300>; > }; > }; > + > + - | > + pinctrl: pinctrl@812c0000 { The unit address does not match the first reg property. > + compatible = "renesas,pfc-r9a09g077"; > + reg = <0x802c0000 0x2000>, > + <0x812c0000 0x2000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pinctrl 0 0 287>; GPIOs without interrupts? > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H 2025-05-26 17:02 ` Geert Uytterhoeven @ 2025-06-02 7:11 ` Lad, Prabhakar 2025-06-02 7:37 ` Geert Uytterhoeven 0 siblings, 1 reply; 6+ messages in thread From: Lad, Prabhakar @ 2025-06-02 7:11 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Thierry Bultel, thierry.bultel, linux-renesas-soc, paul.barker.ct, linux-gpio, devicetree, linux-kernel Hi Geert, Thank you for the review. On Mon, May 26, 2025 at 6:03 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Thierry, > > On Mon, 19 May 2025 at 23:57, Thierry Bultel > <thierry.bultel.yh@bp.renesas.com> wrote: > > Document RZ/T2H (a.k.a r9a09g077) pinctrl > > > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > > @@ -29,6 +29,7 @@ properties: > > - renesas,pfc-r8a774b1 # RZ/G2N > > - renesas,pfc-r8a774c0 # RZ/G2E > > - renesas,pfc-r8a774e1 # RZ/G2H > > + - renesas,pfc-r9a09g077 # RZ/T2H > > - renesas,pfc-r8a7778 # R-Car M1 > > - renesas,pfc-r8a7779 # R-Car H1 > > - renesas,pfc-r8a7790 # R-Car H2 > > From a quick glance at the docs and driver, adding support for RZ/T2H > to this DT binding is a not good match, as the RZ/T2H PFC hardware > does not have the concept of pin groups and functions. > > Using separate DT bindings, as for most other SoCs in the RZ family, > also allows you to use the preferred order "renesas,r9a09g077-<foo>". > Agreed, this needs a separate DT binding file. > > @@ -194,3 +209,13 @@ examples: > > power-source = <3300>; > > }; > > }; > > + > > + - | > > + pinctrl: pinctrl@812c0000 { > > The unit address does not match the first reg property. > > > + compatible = "renesas,pfc-r9a09g077"; > > + reg = <0x802c0000 0x2000>, > > + <0x812c0000 0x2000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pinctrl 0 0 287>; > > GPIOs without interrupts? > I think the intention here was to go without interrupt support for the initial series and when later support for ICU is added we add this property. Hope thats OK? Cheers, Prabhakar ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H 2025-06-02 7:11 ` Lad, Prabhakar @ 2025-06-02 7:37 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2025-06-02 7:37 UTC (permalink / raw) To: Lad, Prabhakar Cc: Thierry Bultel, thierry.bultel, linux-renesas-soc, paul.barker.ct, linux-gpio, devicetree, linux-kernel Hi Prabhakar, On Mon, 2 Jun 2025 at 09:12, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Mon, May 26, 2025 at 6:03 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Mon, 19 May 2025 at 23:57, Thierry Bultel > > <thierry.bultel.yh@bp.renesas.com> wrote: > > > Document RZ/T2H (a.k.a r9a09g077) pinctrl > > > > > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> > > > > > --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml > > > @@ -194,3 +209,13 @@ examples: > > > power-source = <3300>; > > > }; > > > }; > > > + > > > + - | > > > + pinctrl: pinctrl@812c0000 { > > > > The unit address does not match the first reg property. > > > > > + compatible = "renesas,pfc-r9a09g077"; > > > + reg = <0x802c0000 0x2000>, > > > + <0x812c0000 0x2000>; > > > + gpio-controller; > > > + #gpio-cells = <2>; > > > + gpio-ranges = <&pinctrl 0 0 287>; > > > > GPIOs without interrupts? > > > I think the intention here was to go without interrupt support for the > initial series and when later support for ICU is added we add this > property. Hope thats OK? Yes, that is fine. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC [not found] <20250519215734.577053-1-thierry.bultel.yh@bp.renesas.com> 2025-05-19 21:57 ` [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H Thierry Bultel @ 2025-05-19 21:57 ` Thierry Bultel 2025-05-28 11:50 ` Geert Uytterhoeven 1 sibling, 1 reply; 6+ messages in thread From: Thierry Bultel @ 2025-05-19 21:57 UTC (permalink / raw) To: thierry.bultel Cc: linux-renesas-soc, geert, paul.barker.ct, Thierry Bultel, devicetree, linux-kernel Add pinctrl node for r9a09g077 Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 48b889da9095..5648071660ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -101,6 +101,15 @@ cpg: clock-controller@80280000 { #power-domain-cells = <0>; }; + pinctrl: pinctrl@812c0000 { + compatible = "renesas,pfc-r9a09g077"; + reg = <0 0x802c0000 0 0x2000>, + <0 0x812c0000 0 0x2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 287>; + }; + gic: interrupt-controller@83000000 { compatible = "arm,gic-v3"; reg = <0x0 0x83000000 0 0x40000>, -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC 2025-05-19 21:57 ` [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC Thierry Bultel @ 2025-05-28 11:50 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2025-05-28 11:50 UTC (permalink / raw) To: Thierry Bultel Cc: thierry.bultel, linux-renesas-soc, paul.barker.ct, devicetree, linux-kernel Hi Thierry, On Mon, 19 May 2025 at 23:57, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote: > Add pinctrl node for r9a09g077 > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > @@ -101,6 +101,15 @@ cpg: clock-controller@80280000 { > #power-domain-cells = <0>; > }; > > + pinctrl: pinctrl@812c0000 { The unit address does not match the first reg property. > + compatible = "renesas,pfc-r9a09g077"; > + reg = <0 0x802c0000 0 0x2000>, > + <0 0x812c0000 0 0x2000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pinctrl 0 0 287>; No (optional?) clock, no interrupts... > + }; > + > gic: interrupt-controller@83000000 { > compatible = "arm,gic-v3"; > reg = <0x0 0x83000000 0 0x40000>, Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <20250519215734.577053-1-thierry.bultel.yh@bp.renesas.com>
2025-05-19 21:57 ` [PATCH 1/3] dt-bindings: pinctrl: add compatible for Renesas RZ/T2H Thierry Bultel
2025-05-26 17:02 ` Geert Uytterhoeven
2025-06-02 7:11 ` Lad, Prabhakar
2025-06-02 7:37 ` Geert Uytterhoeven
2025-05-19 21:57 ` [PATCH 3/3] arm64: dts: renesas: Add pinctrl for renesas RZ/T2H SoC Thierry Bultel
2025-05-28 11:50 ` Geert Uytterhoeven
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