From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E87ECDFA1 for ; Tue, 25 Oct 2022 12:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231614AbiJYMlB (ORCPT ); Tue, 25 Oct 2022 08:41:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231378AbiJYMlA (ORCPT ); Tue, 25 Oct 2022 08:41:00 -0400 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E82D185425; Tue, 25 Oct 2022 05:40:59 -0700 (PDT) Received: by mail-qk1-f175.google.com with SMTP id 8so7909888qka.1; Tue, 25 Oct 2022 05:40:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Lao/ypUUNI0LjIKEvGEpGGZT7cntnLS2PFomcQrERvE=; b=isKE4M3Ed15PP3W2RI9Xgl09g+mee7lta8lrAXvRWga5CRrE+vESEEnLhZi+omNHaQ DPRj/DoXeqnLeHe85RnlmgVFl1W1yhkOVGvTG6FZ5aPwZ41GhDlJ4I69GP8VrmaCkcLB O8a++ioqdZ/xcx1qks59yo8rnf7HadckRpnuoTD0PMqjYo5LCCepgyU6xClkPuzUNvIz IYAzd3IzK+lScBLuCsoGc5WquYuxA+DMKWQxxw8k+9ojH/wg/g3gPajstPFliCJHM9Bd cuHqYSbzBgNVW0YQ006s4fMrbikHvgimxNBkEYUiBQqA/3X28OC5yH+0OgwpkU6Srga9 XP0w== X-Gm-Message-State: ACrzQf26KjDuz4b/u5uA7YwjnpCuVx3UNLJm+yPl6HY5+t35jrj7xHxW BHBUKDcDm28gOP8vVPC6LNePYpIJFiK5Nw== X-Google-Smtp-Source: AMsMyM7MsvRpNJJYaxWIj/JGMMdI8VbctEcpSCeueXrEDTD2qjlQ7VI6zTZEqU1ktt+xkO7jIGg4mQ== X-Received: by 2002:a37:b802:0:b0:6ee:9495:9a79 with SMTP id i2-20020a37b802000000b006ee94959a79mr25672278qkf.136.1666701657782; Tue, 25 Oct 2022 05:40:57 -0700 (PDT) Received: from mail-yb1-f174.google.com (mail-yb1-f174.google.com. [209.85.219.174]) by smtp.gmail.com with ESMTPSA id d19-20020a05620a241300b006cfc01b4461sm1975292qkn.118.2022.10.25.05.40.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Oct 2022 05:40:57 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id o70so14386009yba.7; Tue, 25 Oct 2022 05:40:57 -0700 (PDT) X-Received: by 2002:a25:4fc2:0:b0:6be:afb4:d392 with SMTP id d185-20020a254fc2000000b006beafb4d392mr31753639ybb.604.1666701657095; Tue, 25 Oct 2022 05:40:57 -0700 (PDT) MIME-Version: 1.0 References: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 25 Oct 2022 14:40:45 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts To: Prabhakar Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Samuel Holland , linux-riscv , Linux ARM , Linux-Renesas , DT , LKML , Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Prabhakar, On Thu, Sep 29, 2022 at 7:24 PM Prabhakar wrote: > This patch series aims to split up the RZ/G2UL SoC DTSI into common parts > so that this can be shared with the RZ/Five SoC. > > Implementation is based on the discussion [0] where I have used option#2. > > The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same > identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is > created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five > (r9a07g043F.dtsi) Thanks for your series! > r9a07g043f.dtsi will look something like below: > > #include > > #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32) > #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na Originally, when I assumed incorrectly that dtc does not support arithmetic, I used "nr" and "na" in the macro I proposed to mean RISC-V ("r") resp. ARM ("a") interrupt number. Apparently the names stuck, although the second parameter now has a completely different meaning ;-) However, as the NCEPLIC does support interrupt flags, unlike the SiFive PLIC, there is no need to have the flags parameter in the macro. Moreover, it looks like the SOC_PERIPHERAL_IRQ_NUMBER() intermediate is not needed, so you can just write: #define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > #include > > / { > ... > ... > }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds