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[209.85.219.52]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-7220f78b9bfsm51176816d6.64.2025.09.05.00.09.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Sep 2025 00:09:45 -0700 (PDT) Received: by mail-qv1-f52.google.com with SMTP id 6a1803df08f44-729c1074875so11419056d6.0; Fri, 05 Sep 2025 00:09:45 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVs2mVtD8nhY8MFjapE9/CazRiXosDgk74/85T09sUKWQ4h7hk4Gxao7cWNoLevvZ7S1ugI/MkQQ3W4jdBx@vger.kernel.org, AJvYcCVvudR+2pzZZIWv8SJc1ciU8YDMlwdgIlBOS3WsO5E+AGjVk4uLGEtWCftYW0wAsJg9AoFkeTMt@vger.kernel.org, AJvYcCXCzxNHiFG4skWqYm307b+PnmkT/4OgcPhJOXmfFWtUg7fOZs4TqGIa70BQLTx+AEk+AtpLTzvMA/Um@vger.kernel.org, AJvYcCXmafFXhd+wRsskwO18ihbKOa2upitE+XW37FnaSOzXHKbGqOCXYwzIKfuf6+wIR7rgZKtgiL2wbIISWRcnuR/uaYk=@vger.kernel.org X-Received: by 2002:a05:6102:4412:b0:508:aeba:ac31 with SMTP id ada2fe7eead31-52b198509ddmr7249793137.2.1757055766011; Fri, 05 Sep 2025 00:02:46 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250904114204.4148520-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250904114204.4148520-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <021e970a-f606-4702-9f0e-b4b0576bc5d6@lunn.ch> In-Reply-To: <021e970a-f606-4702-9f0e-b4b0576bc5d6@lunn.ch> From: Geert Uytterhoeven Date: Fri, 5 Sep 2025 09:02:35 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXwI-xpP3iIVZZhI0fQdOQYz6cBywMUyW9k6_qQbTcQY9MOz59KPn3SE_zo Message-ID: Subject: Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific To: Andrew Lunn Cc: Prabhakar , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Hi Andrew, On Thu, 4 Sept 2025 at 22:37, Andrew Lunn wrote: > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Move the hardcoded switch mode mask definition into the SoC-specific > > miic_of_data structure. This allows each SoC to define its own mask > > value rather than relying on a single fixed constant. For RZ/N1 the > > mask remains GENMASK(4, 0). > > > > This is in preparation for adding support for RZ/T2H, where the > > switch mode mask is GENMASK(2, 0). > > > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) > > > miic_reg_writel(miic, MIIC_MODCTRL, > > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); > > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); > > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So > this __ffs() is pointless. > > You might however want to add a comment that this assumption is being > made. I guess Prabhakar did it this way to make it easier to find candidates for a future conversion to field_prep(), if this ever becomes available[1]. [1] "[PATCH v3 0/4] Non-const bitfield helpers" https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds