[PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support

[PATCH 00/11] Add RZ/G3E USB3.2 Gen1 Host Controller support

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add RZ/G3E USB3.2 Gen1 Host Controller and PHY support. The USB3HOST
is compliant with the Universal Serial Bus 3.2 Specification Revision 1.0.
 - Supports 1 downstream USB receptacles
     - Number of SSP Gen2 or SS ports: 1
     - Number of HS or FS or LS ports: 1
 - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
   High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
 - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
   these split-transactions.
 - Supports Power Control and Over Current Detection.

Biju Das (11):
  dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
  clk: renesas: r9a09g047: Add USB3.0 clocks/resets
  dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
  phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
  usb: host: xhci-rcar: Move R-Car reg definitions
  dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
  usb: host: xhci-plat: Add .post_resume_quirk for struct xhci_plat_priv
  usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support
  arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes
  arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST
  arm64: defconfig: Enable RZ/G3E USB3 PHY driver

 .../bindings/phy/renesas,rzg3e-usb3-phy.yaml  |  63 +++++
 .../bindings/usb/renesas,rzg3e-xhci.yaml      |  84 ++++++
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  30 +++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |  10 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |   8 +
 arch/arm64/configs/defconfig                  |   1 +
 drivers/clk/renesas/r9a09g047-cpg.c           |   9 +-
 drivers/phy/renesas/Kconfig                   |   7 +
 drivers/phy/renesas/Makefile                  |   1 +
 drivers/phy/renesas/phy-rzg3e-usb3.c          | 249 ++++++++++++++++++
 drivers/usb/host/Kconfig                      |   2 +-
 drivers/usb/host/xhci-plat.c                  |  14 +
 drivers/usb/host/xhci-plat.h                  |   1 +
 drivers/usb/host/xhci-rcar-regs.h             |  49 ++++
 drivers/usb/host/xhci-rcar.c                  | 100 +++----
 drivers/usb/host/xhci-rzg3e-regs.h            |  12 +
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |   2 +
 17 files changed, 596 insertions(+), 46 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
 create mode 100644 drivers/phy/renesas/phy-rzg3e-usb3.c
 create mode 100644 drivers/usb/host/xhci-rcar-regs.h
 create mode 100644 drivers/usb/host/xhci-rzg3e-regs.h

-- 
2.43.0

[PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..f165df8a6f5a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
 #define R9A09G047_SPI_CLK_SPI			9
 #define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
+#define R9A09G047_USB3_0_REF_ALT_CLK_P		12
+#define R9A09G047_USB3_0_CLKCORE		13
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
-- 
2.43.0

[PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document Renesas RZ/G3E USB3.0 PHY. This IP is connected between
USB3HOST and PHY module. The main functions of the module are
as follows:
 - Reset control
 - Control of PHY input pins
 - Monitoring of PHY output pins

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/phy/renesas,rzg3e-usb3-phy.yaml  | 63 +++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
new file mode 100644
index 000000000000..b86dc7a291a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.0 PHY
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+  compatible:
+    const: renesas,r9a09g047-usb3-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: APB bus clock
+      - description: USB 2.0 PHY reference clock
+      - description: USB 3.0 PHY reference clock
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: core
+      - const: ref_alt_clk_p
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  '#phy-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+    usb-phy@15870000 {
+        compatible = "renesas,r9a09g047-usb3-phy";
+        reg = <0x15870000 0x10000>;
+        clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
+        clock-names = "pclk", "core", "ref_alt_clk_p";
+        power-domains = <&cpg>;
+        resets = <&cpg 0xaa>;
+        #phy-cells = <0>;
+    };
-- 
2.43.0

[PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
Revision 1.0.
 - Supports 1 downstream USB receptacles
     - Number of SSP Gen2 or SS ports: 1
     - Number of HS or FS or LS ports: 1
 - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
   High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
 - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
   these split-transactions.
 - Supports Power Control and Over Current Detection.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/usb/renesas,rzg3e-xhci.yaml      | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml

diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
new file mode 100644
index 000000000000..2f73ea2e1e78
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.2 Gen2 Host controller
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+  compatible:
+    const: renesas,r9a09g047-xhci
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Logical OR of all interrupt signals.
+      - description: System management interrupt
+      - description: Host system error interrupt
+      - description: Power management event interrupt
+      - description: xHC interrupt
+
+  interrupt-names:
+    items:
+      - const: all
+      - const: smi
+      - const: hse
+      - const: pme
+      - const: xhc
+
+  clocks:
+    maxItems: 1
+
+  phys:
+    maxItems: 2
+
+  phy-names:
+    items:
+      - const: usb2-phy
+      - const: usb3-phy
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - power-domains
+  - resets
+  - phys
+  - phy-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    usb@15850000 {
+      compatible = "renesas,r9a09g047-xhci";
+      reg = <0x15850000 0x10000>;
+      interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-names = "all", "smi", "hse", "pme", "xhc";
+      clocks = <&cpg CPG_MOD 0xaf>;
+      power-domains = <&cpg>;
+      resets = <&cpg 0xaa>;
+      phys = <&usb3_phy>, <&usb3_phy>;
+      phy-names = "usb2-phy", "usb3-phy";
+    };
-- 
2.43.0

[PATCH 09/11] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add USB3 PHY/Host nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e5b24e46d645..b3ef0c15e62d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -836,6 +836,36 @@ gic: interrupt-controller@14900000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		xhci: usb@15850000 {
+			compatible = "renesas,r9a09g047-xhci";
+			reg = <0 0x15850000 0 0x10000>;
+			interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "all", "smi", "hse", "pme", "xhc";
+			clocks = <&cpg CPG_MOD 0xaf>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xaa>;
+			phys = <&usb3_phy>, <&usb3_phy>;
+			phy-names = "usb2-phy", "usb3-phy";
+			status = "disabled";
+		};
+
+		usb3_phy: usb-phy@15870000 {
+			compatible = "renesas,r9a09g047-usb3-phy";
+			reg = <0 0x15870000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xb0>,
+				 <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>,
+				 <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>;
+			clock-names = "pclk", "core", "ref_alt_clk_p";
+			power-domains = <&cpg>;
+			resets = <&cpg 0xaa>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhi0: mmc@15c00000  {
 			compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
 			reg = <0x0 0x15c00000 0 0x10000>;
-- 
2.43.0

[PATCH 10/11] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Enable USB3.2 Gen2 Host controller(a.k.a USB3HOST) on the RZ/G3E SMARC EVK
platform.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 10 ++++++++++
 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi    |  8 ++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..0fd90d79b020 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -164,6 +164,11 @@ sd1-data {
 				 <RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
 		};
 	};
+
+	usb3_pins: usb3 {
+		pinmux = <RZG3E_PORT_PINMUX(4, 1, 12)>, /* USB30_VBUSEN */
+			 <RZG3E_PORT_PINMUX(4, 0, 12)>; /* USB30_OVRCURN */
+	};
 };
 
 &scif0 {
@@ -179,3 +184,8 @@ &sdhi1 {
 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&vqmmc_sd1_pvdd>;
 };
+
+&xhci {
+	pinctrl-0 = <&usb3_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 58561da3007a..8b3765b8267d 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -106,3 +106,11 @@ &sdhi1 {
 
 	status = "okay";
 };
+
+&usb3_phy {
+	status = "okay";
+};
+
+&xhci {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Conor Dooley]

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On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
> Revision 1.0.
>  - Supports 1 downstream USB receptacles
>      - Number of SSP Gen2 or SS ports: 1
>      - Number of HS or FS or LS ports: 1
>  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
>    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
>  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
>    these split-transactions.
>  - Supports Power Control and Over Current Detection.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> +---
> +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#

> +    const: renesas,r9a09g047-xhci

How come these don't match? I don't understand your naming scheme at
all, so idk which is even correct!

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Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 274 bytes --]

On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Now that I look again, same applies here with the different filename and
compatible. Copypaste mistake? Or why does the compatible not match the
filename?



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RE: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Biju Das]

Hi Conor,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 20 August 2025 21:11
> Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> 
> On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > Specification Revision 1.0.
> >  - Supports 1 downstream USB receptacles
> >      - Number of SSP Gen2 or SS ports: 1
> >      - Number of HS or FS or LS ports: 1
> >  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> >    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> >  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> >    these split-transactions.
> >  - Supports Power Control and Over Current Detection.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> > +---
> > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> 
> > +    const: renesas,r9a09g047-xhci
> 
> How come these don't match? I don't understand your naming scheme at all, so idk which is even correct!

r9a09g047 is SoC part number which also known as RZ/G3E SoC.

I just followed the convention used in [1] and [2].
Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f

[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8

Cheers,
Biju

RE: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Biju Das]

Hi Conor,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 20 August 2025 21:13
> Subject: Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
> 
> On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Now that I look again, same applies here with the different filename and compatible. Copypaste mistake?
> Or why does the compatible not match the filename?
> 

r9a09g047 is SoC part number which also known as RZ/G3E SoC.

I just followed the convention used in [1] and [2].
Please let me know, should I change rzg3e-usb3-phy.yaml.yaml-> r9a09g047-usb3-phy.yaml ?

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f

[2]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8

Cheers,
Biju

Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Conor Dooley]

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On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> Hi Conor,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 20 August 2025 21:11
> > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> > 
> > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > Specification Revision 1.0.
> > >  - Supports 1 downstream USB receptacles
> > >      - Number of SSP Gen2 or SS ports: 1
> > >      - Number of HS or FS or LS ports: 1
> > >  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > >    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > >  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > >    these split-transactions.
> > >  - Supports Power Control and Over Current Detection.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > 
> > > +---
> > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> > 
> > > +    const: renesas,r9a09g047-xhci
> > 
> > How come these don't match? I don't understand your naming scheme at all, so idk which is even correct!
> 
> r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> 
> I just followed the convention used in [1] and [2].
> Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?

What's the benefit of using that instead of the compatible, other than
confusing me?

> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=44b91d61c505863b8ae90b7094aee5ca0dce808f
> 
> [2]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?h=next-20250820&id=b2d25905366b4e6791f60e6bc76a636d1b88e6f8
> 
> Cheers,
> Biju

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RE: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Biju Das]

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 21 August 2025 19:16
> Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> 
> On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> > Hi Conor,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 20 August 2025 21:11
> > > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E
> > > USB3HOST
> > >
> > > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > > Specification Revision 1.0.
> > > >  - Supports 1 downstream USB receptacles
> > > >      - Number of SSP Gen2 or SS ports: 1
> > > >      - Number of HS or FS or LS ports: 1
> > > >  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > > >    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > > >  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > > >    these split-transactions.
> > > >  - Supports Power Control and Over Current Detection.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > > +---
> > > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> > >
> > > > +    const: renesas,r9a09g047-xhci
> > >
> > > How come these don't match? I don't understand your naming scheme at all, so idk which is even
> correct!
> >
> > r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> >
> > I just followed the convention used in [1] and [2].
> > Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
> 
> What's the benefit of using that instead of the compatible, other than confusing me?

I guess, for an end user it will be useful to locate the document easily without any issue

Given a choice to locate a document rzg3e-xhci.yaml vs r9a09g047-xhci.yaml which one you prefer
for RZ/G3E XHCI IP?

Cheers,
Biju

Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY

[Rob Herring]

On Thu, Aug 21, 2025 at 07:18:59AM +0000, Biju Das wrote:
> Hi Conor,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 20 August 2025 21:13
> > Subject: Re: [PATCH 03/11] dt-bindings: phy: renesas: Document Renesas RZ/G3E USB3.0 PHY
> > 
> > On Wed, Aug 20, 2025 at 09:10:07PM +0100, Conor Dooley wrote:
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > Now that I look again, same applies here with the different filename and compatible. Copypaste mistake?
> > Or why does the compatible not match the filename?
> > 
> 
> r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> 
> I just followed the convention used in [1] and [2].
> Please let me know, should I change rzg3e-usb3-phy.yaml.yaml-> r9a09g047-usb3-phy.yaml ?

I think it is fine as-is.

Rob

Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Rob Herring]

On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> The USB3HOST is compliant with the Universal Serial Bus 3.2 Specification
> Revision 1.0.
>  - Supports 1 downstream USB receptacles
>      - Number of SSP Gen2 or SS ports: 1
>      - Number of HS or FS or LS ports: 1
>  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
>    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
>  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
>    these split-transactions.
>  - Supports Power Control and Over Current Detection.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/usb/renesas,rzg3e-xhci.yaml      | 84 +++++++++++++++++++
>  1 file changed, 84 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
> new file mode 100644
> index 000000000000..2f73ea2e1e78
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/renesas,rzg3e-xhci.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3E USB 3.2 Gen2 Host controller
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +

Common USB and XHCI properties don't apply?

> +properties:
> +  compatible:
> +    const: renesas,r9a09g047-xhci
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: Logical OR of all interrupt signals.
> +      - description: System management interrupt
> +      - description: Host system error interrupt
> +      - description: Power management event interrupt
> +      - description: xHC interrupt
> +
> +  interrupt-names:
> +    items:
> +      - const: all
> +      - const: smi
> +      - const: hse
> +      - const: pme
> +      - const: xhc
> +
> +  clocks:
> +    maxItems: 1
> +
> +  phys:
> +    maxItems: 2
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - power-domains
> +  - resets
> +  - phys
> +  - phy-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    usb@15850000 {
> +      compatible = "renesas,r9a09g047-xhci";
> +      reg = <0x15850000 0x10000>;
> +      interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
> +      interrupt-names = "all", "smi", "hse", "pme", "xhc";
> +      clocks = <&cpg CPG_MOD 0xaf>;
> +      power-domains = <&cpg>;
> +      resets = <&cpg 0xaa>;
> +      phys = <&usb3_phy>, <&usb3_phy>;
> +      phy-names = "usb2-phy", "usb3-phy";
> +    };
> -- 
> 2.43.0
> 

Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST

[Conor Dooley]

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On Fri, Aug 22, 2025 at 06:48:07AM +0000, Biju Das wrote:
> Hi Conor,
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 21 August 2025 19:16
> > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
> > 
> > On Thu, Aug 21, 2025 at 07:15:59AM +0000, Biju Das wrote:
> > > Hi Conor,
> > >
> > > Thanks for the feedback.
> > >
> > > > -----Original Message-----
> > > > From: Conor Dooley <conor@kernel.org>
> > > > Sent: 20 August 2025 21:11
> > > > Subject: Re: [PATCH 06/11] dt-bindings: usb: Document Renesas RZ/G3E
> > > > USB3HOST
> > > >
> > > > On Wed, Aug 20, 2025 at 06:17:53PM +0100, Biju wrote:
> > > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > >
> > > > > Document the Renesas RZ/G3E USB3.2 Gen2 Host Controller (a.k.a USB3HOST).
> > > > > The USB3HOST is compliant with the Universal Serial Bus 3.2
> > > > > Specification Revision 1.0.
> > > > >  - Supports 1 downstream USB receptacles
> > > > >      - Number of SSP Gen2 or SS ports: 1
> > > > >      - Number of HS or FS or LS ports: 1
> > > > >  - Supports Super Speed Plus Gen2x1 (10 Gbps), Super Speed (5 Gbps),
> > > > >    High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5 Mbps).
> > > > >  - Supports all transfer-types: Control, Bulk, Interrupt, Isochronous, and
> > > > >    these split-transactions.
> > > > >  - Supports Power Control and Over Current Detection.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/usb/renesas,rzg3e-xhci.yaml#
> > > >
> > > > > +    const: renesas,r9a09g047-xhci
> > > >
> > > > How come these don't match? I don't understand your naming scheme at all, so idk which is even
> > correct!
> > >
> > > r9a09g047 is SoC part number which also known as RZ/G3E SoC.
> > >
> > > I just followed the convention used in [1] and [2].
> > > Please let me know I should change rzg3e-xhci.yaml->r9a09g047-xhci.yaml ?
> > 
> > What's the benefit of using that instead of the compatible, other than confusing me?
> 
> I guess, for an end user it will be useful to locate the document easily without any issue

If you're looking to avoid issues for end users, why are you mixing and
matching at all between the part number and the codename or w/e RZ/G3E
is?

> Given a choice to locate a document rzg3e-xhci.yaml vs r9a09g047-xhci.yaml which one you prefer
> for RZ/G3E XHCI IP?

My preference is filenames matching compatibles as the norm, but
apparently Rob doesn't give care in this case nor does Krzysztof
(seeing as they acked/applied similar stuff for the platform already) so I
won't dig my heels in.

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Re: [PATCH 01/11] dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks

[Geert Uytterhoeven]

On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
> header file.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds