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[209.85.128.175]) by smtp.gmail.com with ESMTPSA id x8-20020a05620a258800b006b9a89d408csm1099751qko.100.2022.08.18.02.39.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Aug 2022 02:39:04 -0700 (PDT) Received: by mail-yw1-f175.google.com with SMTP id 00721157ae682-32a09b909f6so27160447b3.0; Thu, 18 Aug 2022 02:39:03 -0700 (PDT) X-Received: by 2002:a25:250b:0:b0:68f:425b:3ee0 with SMTP id l11-20020a25250b000000b0068f425b3ee0mr2056784ybl.89.1660815543145; Thu, 18 Aug 2022 02:39:03 -0700 (PDT) MIME-Version: 1.0 References: <20220710115248.190280-1-biju.das.jz@bp.renesas.com> <20220710115248.190280-3-biju.das.jz@bp.renesas.com> In-Reply-To: <20220710115248.190280-3-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 18 Aug 2022 11:38:52 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 2/6] dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} support To: Biju Das Cc: Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Biju, On Sun, Jul 10, 2022 at 1:53 PM Biju Das wrote: > Add CAN binding documentation for Renesas RZ/N1 SoC. > > The SJA1000 CAN controller on RZ/N1 SoC has some differences compared > to others like it has no clock divider register (CDR) support and it has > no HW loopback (HW doesn't see tx messages on rx), so introduced a new > compatible 'renesas,rzn1-sja1000' to handle these differences. > > Signed-off-by: Biju Das Thanks for your patch, which is now commit 4591c760b7975984 ("dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} in v6.0-rc1. > --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml > @@ -11,9 +11,15 @@ maintainers: > > properties: > compatible: > - enum: > - - nxp,sja1000 > - - technologic,sja1000 > + oneOf: > + - enum: > + - nxp,sja1000 > + - technologic,sja1000 > + - items: > + - enum: > + - renesas,r9a06g032-sja1000 # RZ/N1D > + - renesas,r9a06g033-sja1000 # RZ/N1S > + - const: renesas,rzn1-sja1000 # RZ/N1 > > reg: > maxItems: 1 > @@ -21,6 +27,9 @@ properties: > interrupts: > maxItems: 1 > > + clocks: > + maxItems: 1 > + Probably you want to add the power-domains property, and make it required on RZ/N1. This is not super-critical, as your driver patch uses explicit clock handling anyway. > reg-io-width: > $ref: /schemas/types.yaml#/definitions/uint32 > description: I/O register width (in bytes) implemented by this device Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds