* [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-07-03 9:45 ` Geert Uytterhoeven
2025-06-25 15:30 ` [PATCH 2/6] arm64: dts: renesas: r9a09g087: " Prabhakar
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/T2H ("R9A09G077") SoC includes three I2C (RIIC) channels.
Adds the device tree nodes for all three I2C controllers to RZ/T2H
SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 45 ++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 42c3b86196d6..eec6fec19944 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -90,6 +90,51 @@ sci0: serial@80005000 {
status = "disabled";
};
+ i2c0: i2c@80088000 {
+ compatible = "renesas,riic-r9a09g077";
+ reg = <0 0x80088000 0 0x400>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 100>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@80088004 {
+ compatible = "renesas,riic-r9a09g077";
+ reg = <0 0x80088400 0 0x400>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 101>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@81008000 {
+ compatible = "renesas,riic-r9a09g077";
+ reg = <0 0x81008000 0 0x400>;
+ interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 501>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes
2025-06-25 15:30 ` [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes Prabhakar
@ 2025-07-03 9:45 ` Geert Uytterhoeven
2025-07-03 23:51 ` Lad, Prabhakar
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-03 9:45 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Wed, 25 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/T2H ("R9A09G077") SoC includes three I2C (RIIC) channels.
> Adds the device tree nodes for all three I2C controllers to RZ/T2H
> SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -90,6 +90,51 @@ sci0: serial@80005000 {
> status = "disabled";
> };
>
> + i2c0: i2c@80088000 {
> + compatible = "renesas,riic-r9a09g077";
> + reg = <0 0x80088000 0 0x400>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 100>;
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@80088004 {
80088400
Aha, the related warning was demoted to W=1:
Warning (simple_bus_reg): /soc/i2c@80088004: simple-bus unit
address format error, expected "80088400"
> + compatible = "renesas,riic-r9a09g077";
> + reg = <0 0x80088400 0 0x400>;
> + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 101>;
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@81008000 {
> + compatible = "renesas,riic-r9a09g077";
> + reg = <0 0x81008000 0 0x400>;
> + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 501>;
601
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> cpg: clock-controller@80280000 {
> compatible = "renesas,r9a09g077-cpg-mssr";
> reg = <0 0x80280000 0 0x1000>,
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes
2025-07-03 9:45 ` Geert Uytterhoeven
@ 2025-07-03 23:51 ` Lad, Prabhakar
0 siblings, 0 replies; 18+ messages in thread
From: Lad, Prabhakar @ 2025-07-03 23:51 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Thu, Jul 3, 2025 at 10:45 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 25 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The Renesas RZ/T2H ("R9A09G077") SoC includes three I2C (RIIC) channels.
> > Adds the device tree nodes for all three I2C controllers to RZ/T2H
> > SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > @@ -90,6 +90,51 @@ sci0: serial@80005000 {
> > status = "disabled";
> > };
> >
> > + i2c0: i2c@80088000 {
> > + compatible = "renesas,riic-r9a09g077";
> > + reg = <0 0x80088000 0 0x400>;
> > + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eei", "rxi", "txi", "tei";
> > + clocks = <&cpg CPG_MOD 100>;
> > + power-domains = <&cpg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@80088004 {
>
> 80088400
>
Agreed.
> Aha, the related warning was demoted to W=1:
>
Thanks for the hint, I always ran it with W=2.
> Warning (simple_bus_reg): /soc/i2c@80088004: simple-bus unit
> address format error, expected "80088400"
>
> > + compatible = "renesas,riic-r9a09g077";
> > + reg = <0 0x80088400 0 0x400>;
> > + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eei", "rxi", "txi", "tei";
> > + clocks = <&cpg CPG_MOD 101>;
> > + power-domains = <&cpg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c@81008000 {
> > + compatible = "renesas,riic-r9a09g077";
> > + reg = <0 0x81008000 0 0x400>;
> > + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eei", "rxi", "txi", "tei";
> > + clocks = <&cpg CPG_MOD 501>;
>
> 601
>
Agreed.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/6] arm64: dts: renesas: r9a09g087: Add I2C controller nodes
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
2025-06-25 15:30 ` [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-07-03 9:50 ` Geert Uytterhoeven
2025-06-25 15:30 ` [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes Prabhakar
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/N2H ("R9A09G087") SoC includes three I2C (RIIC) channels.
Adds the device tree nodes for all three I2C controllers to RZ/N2H
SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 45 ++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index e57a91adcb68..63c9681116bf 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -90,6 +90,51 @@ sci0: serial@80005000 {
status = "disabled";
};
+ i2c0: i2c@80088000 {
+ compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
+ reg = <0 0x80088000 0 0x400>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 100>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@80088004 {
+ compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
+ reg = <0 0x80088400 0 0x400>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 101>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@81008000 {
+ compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
+ reg = <0 0x81008000 0 0x400>;
+ interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eei", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 501>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 2/6] arm64: dts: renesas: r9a09g087: Add I2C controller nodes
2025-06-25 15:30 ` [PATCH 2/6] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-07-03 9:50 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-03 9:50 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The Renesas RZ/N2H ("R9A09G087") SoC includes three I2C (RIIC) channels.
> Adds the device tree nodes for all three I2C controllers to RZ/N2H
> SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -90,6 +90,51 @@ sci0: serial@80005000 {
> status = "disabled";
> };
>
> + i2c0: i2c@80088000 {
> + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
> + reg = <0 0x80088000 0 0x400>;
> + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 100>;
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@80088004 {
80088400
> + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
> + reg = <0 0x80088400 0 0x400>;
> + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 101>;
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@81008000 {
> + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
> + reg = <0 0x81008000 0 0x400>;
> + interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eei", "rxi", "txi", "tei";
> + clocks = <&cpg CPG_MOD 501>;
601
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> cpg: clock-controller@80280000 {
> compatible = "renesas,r9a09g087-cpg-mssr";
> reg = <0 0x80280000 0 0x1000>,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
2025-06-25 15:30 ` [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add I2C controller nodes Prabhakar
2025-06-25 15:30 ` [PATCH 2/6] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-07-03 9:55 ` Geert Uytterhoeven
2025-06-25 15:30 ` [PATCH 4/6] arm64: dts: renesas: r9a09g087: " Prabhakar
` (3 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index eec6fec19944..2949790e39a9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ sdhi0: mmc@92080000 {
+ compatible = "renesas,sdhi-r9a09g077",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92080000 0 0x10000>;
+ interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1212>,
+ <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi0_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI0-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
+
+ sdhi1: mmc@92090000 {
+ compatible = "renesas,sdhi-r9a09g077",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92090000 0 0x10000>;
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1213>,
+ <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
};
timer {
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes
2025-06-25 15:30 ` [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes Prabhakar
@ 2025-07-03 9:55 ` Geert Uytterhoeven
2025-07-03 23:52 ` Lad, Prabhakar
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-03 9:55 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> };
> +
> + sdhi0: mmc@92080000 {
> + compatible = "renesas,sdhi-r9a09g077",
> + "renesas,sdhi-r9a09g057";
> + reg = <0x0 0x92080000 0 0x10000>;
> + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1212>,
1112?
> + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
> + clock-names = "aclk", "clkh";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + sdhi0_vqmmc: vqmmc-regulator {
> + regulator-name = "SDHI0-VQMMC";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + status = "disabled";
> + };
> + };
> +
> + sdhi1: mmc@92090000 {
> + compatible = "renesas,sdhi-r9a09g077",
> + "renesas,sdhi-r9a09g057";
> + reg = <0x0 0x92090000 0 0x10000>;
> + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1213>,
1113?
> + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>;
> + clock-names = "aclk", "clkh";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + sdhi1_vqmmc: vqmmc-regulator {
> + regulator-name = "SDHI1-VQMMC";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + status = "disabled";
> + };
> + };
> };
>
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes
2025-07-03 9:55 ` Geert Uytterhoeven
@ 2025-07-03 23:52 ` Lad, Prabhakar
2025-07-04 17:12 ` Lad, Prabhakar
0 siblings, 1 reply; 18+ messages in thread
From: Lad, Prabhakar @ 2025-07-03 23:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> > interrupt-controller;
> > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > };
> > +
> > + sdhi0: mmc@92080000 {
> > + compatible = "renesas,sdhi-r9a09g077",
> > + "renesas,sdhi-r9a09g057";
> > + reg = <0x0 0x92080000 0 0x10000>;
> > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 1212>,
>
> 1112?
>
Agreed (and below).
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes
2025-07-03 23:52 ` Lad, Prabhakar
@ 2025-07-04 17:12 ` Lad, Prabhakar
2025-07-07 9:47 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Lad, Prabhakar @ 2025-07-04 17:12 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Geert,
>
> Thank you for the review.
>
> On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> > > interrupt-controller;
> > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > > };
> > > +
> > > + sdhi0: mmc@92080000 {
> > > + compatible = "renesas,sdhi-r9a09g077",
> > > + "renesas,sdhi-r9a09g057";
> > > + reg = <0x0 0x92080000 0 0x10000>;
> > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&cpg CPG_MOD 1212>,
> >
> > 1112?
> >
> Agreed (and below).
>
Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes
2025-07-04 17:12 ` Lad, Prabhakar
@ 2025-07-07 9:47 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-07 9:47 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Fri, 4 Jul 2025 at 19:13, Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> On Fri, Jul 4, 2025 at 12:52 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Jul 3, 2025 at 10:56 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add SDHI0-SDHI1 nodes to RZ/T2H ("R9A09G077") SoC DTSI.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > > > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> > > > interrupt-controller;
> > > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > > > };
> > > > +
> > > > + sdhi0: mmc@92080000 {
> > > > + compatible = "renesas,sdhi-r9a09g077",
> > > > + "renesas,sdhi-r9a09g057";
> > > > + reg = <0x0 0x92080000 0 0x10000>;
> > > > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&cpg CPG_MOD 1212>,
> > >
> > > 1112?
> > >
> > Agreed (and below).
> >
> Sorry, it is indeed 1212/1213 as the bits belong to MSTPCRM register.
Oops, you're right. Sorry for the noise.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/6] arm64: dts: renesas: r9a09g087: Add SDHI nodes
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
` (2 preceding siblings ...)
2025-06-25 15:30 ` [PATCH 3/6] arm64: dts: renesas: r9a09g077: Add SDHI nodes Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-07-03 9:56 ` Geert Uytterhoeven
2025-06-25 15:30 ` [PATCH 5/6] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs Prabhakar
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add SDHI0-SDHI1 nodes to RZ/N2H ("R9A09G087") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 63c9681116bf..532dcc0d8dd6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ sdhi0: mmc@92080000 {
+ compatible = "renesas,sdhi-r9a09g087",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92080000 0 0x10000>;
+ interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1212>,
+ <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi0_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI0-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
+
+ sdhi1: mmc@92090000 {
+ compatible = "renesas,sdhi-r9a09g087",
+ "renesas,sdhi-r9a09g057";
+ reg = <0x0 0x92090000 0 0x10000>;
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1213>,
+ <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
+ clock-names = "aclk", "clkh";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ sdhi1_vqmmc: vqmmc-regulator {
+ regulator-name = "SDHI1-VQMMC";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+ };
};
timer {
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 4/6] arm64: dts: renesas: r9a09g087: Add SDHI nodes
2025-06-25 15:30 ` [PATCH 4/6] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-07-03 9:56 ` Geert Uytterhoeven
2025-07-07 9:48 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-03 9:56 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add SDHI0-SDHI1 nodes to RZ/N2H ("R9A09G087") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> interrupt-controller;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> };
> +
> + sdhi0: mmc@92080000 {
> + compatible = "renesas,sdhi-r9a09g087",
> + "renesas,sdhi-r9a09g057";
> + reg = <0x0 0x92080000 0 0x10000>;
> + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1212>,
1112?
> + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
> + clock-names = "aclk", "clkh";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + sdhi0_vqmmc: vqmmc-regulator {
> + regulator-name = "SDHI0-VQMMC";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + status = "disabled";
> + };
> + };
> +
> + sdhi1: mmc@92090000 {
> + compatible = "renesas,sdhi-r9a09g087",
> + "renesas,sdhi-r9a09g057";
> + reg = <0x0 0x92090000 0 0x10000>;
> + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 1213>,
1113?
> + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
> + clock-names = "aclk", "clkh";
> + power-domains = <&cpg>;
> + status = "disabled";
> +
> + sdhi1_vqmmc: vqmmc-regulator {
> + regulator-name = "SDHI1-VQMMC";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + status = "disabled";
> + };
> + };
> };
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/6] arm64: dts: renesas: r9a09g087: Add SDHI nodes
2025-07-03 9:56 ` Geert Uytterhoeven
@ 2025-07-07 9:48 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-07-07 9:48 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
On Thu, 3 Jul 2025 at 11:56, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 25 Jun 2025 at 17:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add SDHI0-SDHI1 nodes to RZ/N2H ("R9A09G087") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> > @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 {
> > interrupt-controller;
> > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > };
> > +
> > + sdhi0: mmc@92080000 {
> > + compatible = "renesas,sdhi-r9a09g087",
> > + "renesas,sdhi-r9a09g057";
> > + reg = <0x0 0x92080000 0 0x10000>;
> > + interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 1212>,
>
> 1112?
>
> > + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
> > + clock-names = "aclk", "clkh";
> > + power-domains = <&cpg>;
> > + status = "disabled";
> > +
> > + sdhi0_vqmmc: vqmmc-regulator {
> > + regulator-name = "SDHI0-VQMMC";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > + sdhi1: mmc@92090000 {
> > + compatible = "renesas,sdhi-r9a09g087",
> > + "renesas,sdhi-r9a09g057";
> > + reg = <0x0 0x92090000 0 0x10000>;
> > + interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 1213>,
>
> 1113?
>
> > + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>;
> > + clock-names = "aclk", "clkh";
> > + power-domains = <&cpg>;
> > + status = "disabled";
> > +
> > + sdhi1_vqmmc: vqmmc-regulator {
> > + regulator-name = "SDHI1-VQMMC";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <3300000>;
> > + status = "disabled";
> > + };
> > + };
> > };
> >
Same here: it is indeed 1212/1213 as the bits belong to MSTPCRM register.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/6] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
` (3 preceding siblings ...)
2025-06-25 15:30 ` [PATCH 4/6] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-06-25 15:30 ` [PATCH 6/6] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: " Prabhakar
2025-06-26 14:26 ` [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Geert Uytterhoeven
6 siblings, 0 replies; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add USER LED0-LED8, which are available on RZ/T2H EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 486584fefead..f36a289a4d9c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -7,10 +7,60 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "r9a09g077m44.dtsi"
#include "rzt2h-n2h-evk-common.dtsi"
/ {
model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ /* SW8-9: ON, SW8-10: OFF */
+ gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ led1 {
+ /* SW5-1: OFF, SW5-2: ON */
+ gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ led2 {
+ gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ /* SW2-3: OFF */
+ gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ /* SW8-3: ON, SW8-4: OFF */
+ gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ /* SW8-1: ON, SW8-2: OFF */
+ gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ /* SW5-9: OFF, SW5-10: ON */
+ gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ led7 {
+ /* SW5-7: OFF, SW5-8: ON */
+ gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ led8 {
+ /* SW7-5: OFF, SW7-6: ON */
+ gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_LOW>;
+ };
+ };
};
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6/6] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
` (4 preceding siblings ...)
2025-06-25 15:30 ` [PATCH 5/6] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs Prabhakar
@ 2025-06-25 15:30 ` Prabhakar
2025-06-26 14:26 ` [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Geert Uytterhoeven
6 siblings, 0 replies; 18+ messages in thread
From: Prabhakar @ 2025-06-25 15:30 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add USER LED0-LED8, which are available on RZ/N2H EVK.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index d6ba14a26f03..f6437e82a7de 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -7,10 +7,64 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "r9a09g087m44.dtsi"
#include "rzt2h-n2h-evk-common.dtsi"
/ {
model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+
+ leds {
+ compatible = "gpio-leds";
+
+ led3 {
+ /* DSW18-7: ON, DSW18-8: OFF */
+ gpios = <&pinctrl RZN2H_GPIO(31, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ /* DSW18-9: ON, DSW18-10: OFF */
+ gpios = <&pinctrl RZN2H_GPIO(18, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ /* DSW18-1: ON, DSW18-2: OFF */
+ gpios = <&pinctrl RZN2H_GPIO(22, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ /* DSW18-3: ON, DSW18-4: OFF */
+ gpios = <&pinctrl RZN2H_GPIO(23, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ led7 {
+ /*
+ * DSW18-5: ON, DSW18-6: OFF
+ * DSW19-3: ON, DSW19-4: OFF
+ */
+ gpios = <&pinctrl RZN2H_GPIO(14, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ led8 {
+ /* DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON */
+ gpios = <&pinctrl RZN2H_GPIO(14, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ led9 {
+ /* DSW15-5: OFF, DSW16-6: ON */
+ gpios = <&pinctrl RZN2H_GPIO(14, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ led10 {
+ /* DSW17-3: OFF, DSW17-4: ON */
+ gpios = <&pinctrl RZN2H_GPIO(2, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ led11 {
+ /* DSW17-1: OFF, DSW17-2: ON */
+ gpios = <&pinctrl RZN2H_GPIO(3, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
};
--
2.49.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs
2025-06-25 15:30 [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Prabhakar
` (5 preceding siblings ...)
2025-06-25 15:30 ` [PATCH 6/6] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: " Prabhakar
@ 2025-06-26 14:26 ` Geert Uytterhoeven
2025-06-27 12:53 ` Lad, Prabhakar
6 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2025-06-26 14:26 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Wed, 25 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> This patch series adds I2C and SDHI nodes for the Renesas RZ/T2H
> (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The I2C/SDHI nodes are added
> to the respective SoC DTSI files. Additionally, user LEDs are added
> to the RZ/T2H EVK and RZ/N2H EVK boards.
Thanks for your series!
> Note, these patches apply on top of the series:
> https://lore.kernel.org/all/20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> https://lore.kernel.org/all/20250617162810.154332-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
FTR, the LED patches also depend on:
- Adding the pinctrl nodes,
- Including dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>,
- Adding RZN2H_*() macros.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs
2025-06-26 14:26 ` [PATCH 0/6] arm64: dts: renesas: Add I2C and SDHI nodes for RZ/T2H and RZ/N2H SoCs Geert Uytterhoeven
@ 2025-06-27 12:53 ` Lad, Prabhakar
0 siblings, 0 replies; 18+ messages in thread
From: Lad, Prabhakar @ 2025-06-27 12:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
On Thu, Jun 26, 2025 at 3:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 25 Jun 2025 at 17:30, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > This patch series adds I2C and SDHI nodes for the Renesas RZ/T2H
> > (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The I2C/SDHI nodes are added
> > to the respective SoC DTSI files. Additionally, user LEDs are added
> > to the RZ/T2H EVK and RZ/N2H EVK boards.
>
> Thanks for your series!
>
> > Note, these patches apply on top of the series:
> > https://lore.kernel.org/all/20250617171957.162145-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> > https://lore.kernel.org/all/20250617162810.154332-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>
> FTR, the LED patches also depend on:
> - Adding the pinctrl nodes,
> - Including dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>,
> - Adding RZN2H_*() macros.
>
Oops, thanks for pointing this out. I missed to mention this dependency,
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread