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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id g12-20020a25ef0c000000b00dcd56356c80sm1422691ybd.47.2024.02.27.07.42.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Feb 2024 07:42:07 -0800 (PST) Received: by mail-yb1-f178.google.com with SMTP id 3f1490d57ef6-dbed0710c74so3987152276.1; Tue, 27 Feb 2024 07:42:07 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWfO9wEY764J3VK0NnmS+VTkQP0AFYTR2L5vMuQPjIzDvPJ6Lycky+djp5Jk3CC6Cw0GP14KSOvyzmF6Q4u2nYJmLf+xNJjeAd6qMOTYMQjcvHKzn8XrdLkadou7G68TT1YOPw9q50Tvb+RBmjt/0xtsO/lkkDan/E6aBlNur4hugmS5Su0FY1LleKIREhLOdZ3yMZ8JpX5u7jQYov4PtgeAaE1SeLQp19kxkbzwiFBHnfOugndwJ7/KcAWtpzFAeEZbb2wShKjGGbVSAqo8fLS2uY9uuou03yUNvunllulsLwD20XLvIK0cq8BtR8ATlv1bO4XlWWWkasJNTjM8GVPaRwgBc4ICsAdFpklxyiO7rE/PnIDPro= X-Received: by 2002:a05:6902:2412:b0:dc7:4cb1:6817 with SMTP id dr18-20020a056902241200b00dc74cb16817mr2901377ybb.22.1709048525820; Tue, 27 Feb 2024 07:42:05 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <222dd134b5e1c8cc5baa7afc64a3441a8174e979.1704788539.git.ysato@users.sourceforge.jp> In-Reply-To: <222dd134b5e1c8cc5baa7afc64a3441a8174e979.1704788539.git.ysato@users.sourceforge.jp> From: Geert Uytterhoeven Date: Tue, 27 Feb 2024 16:41:53 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [DO NOT MERGE v6 14/37] clk: Compatible with narrow registers To: Yoshinori Sato Cc: linux-sh@vger.kernel.org, Damien Le Moal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Thomas Gleixner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Yang Xiwen , Sebastian Reichel , Linus Walleij , Randy Dunlap , Arnd Bergmann , Vlastimil Babka , Hyeonggon Yoo <42.hyeyoo@gmail.com>, David Rientjes , Baoquan He , Andrew Morton , Guenter Roeck , Stephen Rothwell , Azeem Shaikh , Javier Martinez Canillas , Max Filippov , Palmer Dabbelt , Bin Meng , Jonathan Corbet , Jacky Huang , Lukas Bulwahn , Biju Das , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Michael Karcher , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Sato-san, On Tue, Jan 9, 2024 at 9:24=E2=80=AFAM Yoshinori Sato wrote: > divider and gate only support 32-bit registers. > Older hardware uses narrower registers, so I want to be able to handle > 8-bit and 16-bit wide registers. > > Seven clk_divider flags are used, and if I add flags for 8bit access and > 16bit access, 8bit will not be enough, so I expanded it to u16. > > Signed-off-by: Yoshinori Sato Thanks for your patch! > --- a/drivers/clk/clk-gate.c > +++ b/drivers/clk/clk-gate.c > @@ -143,6 +161,18 @@ struct clk_hw *__clk_hw_register_gate(struct device = *dev, > return ERR_PTR(-EINVAL); > } Please add a check for invalid CLK_GATE_HIWORD_MASK and register width combinations: if (clk_gate_flags & (CLK_GATE_REG_16BIT | CLK_GATE_REG_8BI= T)) { pr_err("HIWORD_MASK needs 32-bit registers\n"); return ERR_PTR(-EINVAL); } > } > + if (clk_gate_flags & CLK_GATE_REG_16BIT) { > + if (bit_idx > 15) { > + pr_err("gate bit exceeds 16 bits\n"); > + return ERR_PTR(-EINVAL); > + } > + } > + if (clk_gate_flags & CLK_GATE_REG_8BIT) { > + if (bit_idx > 7) { > + pr_err("gate bit exceeds 8 bits\n"); > + return ERR_PTR(-EINVAL); > + } > + } > > /* allocate the gate */ > gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index ace3a4ce2fc9..e2dfc1f083f4 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -508,12 +508,16 @@ void of_fixed_clk_setup(struct device_node *np); > * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are = used for > * the gate register. Setting this flag makes the register accesses= big > * endian. > + * CLK_GATE_REG_8BIT - by default 32bit register accesses are used for > + * the gate register. Setting this flag makes the register accesses= 8bit. > + * CLK_GATE_REG_16BIT - by default 32bit register accesses are used for > + * the gate register. Setting this flag makes the register accesses= 16bit. > */ > struct clk_gate { > struct clk_hw hw; > void __iomem *reg; > u8 bit_idx; > - u8 flags; > + u32 flags; There is no need to increase the size of the flags field for the gate clock= . > spinlock_t *lock; > }; > > @@ -522,6 +526,8 @@ struct clk_gate { > #define CLK_GATE_SET_TO_DISABLE BIT(0) > #define CLK_GATE_HIWORD_MASK BIT(1) > #define CLK_GATE_BIG_ENDIAN BIT(2) > +#define CLK_GATE_REG_8BIT BIT(3) > +#define CLK_GATE_REG_16BIT BIT(4) > > extern const struct clk_ops clk_gate_ops; > struct clk_hw *__clk_hw_register_gate(struct device *dev, The rest LGTM. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds