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[209.85.222.170]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6eec9771c41sm47058866d6.76.2025.03.31.07.11.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Mar 2025 07:11:57 -0700 (PDT) Received: by mail-qk1-f170.google.com with SMTP id af79cd13be357-7c55500d08cso406818085a.0; Mon, 31 Mar 2025 07:11:57 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUuv6ZpXhucxbJAZlMAtYxjQ/zFJLS5zTjFNkZeI+BH0BBqaL4S1m+xLD/guGsyxvGxS5nBtddphDgI@vger.kernel.org, AJvYcCV6SfZTT7lEaCnem9WYrY2X9FVigwcfO/smIs1Bs7QFfub9bBmOOfZNQBSTOLpGAZe/gT52Omiaz6LgW86vgjdAMOc=@vger.kernel.org X-Received: by 2002:a05:620a:1996:b0:7c5:5d9b:b626 with SMTP id af79cd13be357-7c6908af2d8mr1386238985a.36.1743430317561; Mon, 31 Mar 2025 07:11:57 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250311113620.4312-1-biju.das.jz@bp.renesas.com> <20250311113620.4312-2-biju.das.jz@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 31 Mar 2025 16:11:45 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AQ5f1JrfSn58xtLeI1SWXo6l9KENK07iAjtezEEDfiz5_cJxxlK8QwvnC3tJc00 Message-ID: Subject: Re: [PATCH v3 1/9] dt-bindings: memory: Document RZ/G3E support To: Biju Das Cc: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Mark Brown , Magnus Damm , Stephen Boyd , "devicetree@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , Prabhakar Mahadev Lad , "biju.das.au" Content-Type: text/plain; charset="UTF-8" Hi Biju, On Mon, 31 Mar 2025 at 15:54, Biju Das wrote: > > From: Biju Das > > Document support for the Expanded Serial Peripheral Interface (xSPI) Controller in the Renesas RZ/G3E > > (R9A09G047) SoC. > > > > Reviewed-by: Rob Herring (Arm) > > Signed-off-by: Biju Das > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e > > +++ -xspi.yaml > > + spi@11030000 { > > + compatible = "renesas,r9a09g047-xspi"; > > + reg = <0x11030000 0x10000>, <0x20000000 0x10000000>; > > + reg-names = "regs", "dirmap"; > > + interrupts = , > > + ; > > + interrupt-names = "pulse", "err_pulse"; > > + clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>, > > + <&cpg CPG_MOD 0xa1>, <&cpg CPG_MOD 0xa1>; > > On the next version I am going to update spix2 clk as > <&cpg CPG_CORE R9A09G047_SPI_CLK_SPIX2> What's spix2 clk? Ah, re-adding dropped line: > > + clock-names = "ahb", "axi", "spi", "spix2"; > Based on [1], the clk specifier cannot distinguish between > spi and spix2 clk, as entries are same(gating bits). So, treating > spix2 as core clock to distinguish them. > > Please let me know if there are any issues in this approach? As you wrote in [2], you have to check the two monitor register bits together. How do you plan to handle that requirement? > [1] https://lore.kernel.org/all/TY3PR01MB11346B3B6CFF1359411B475A386A62@TY3PR01MB11346.jpnprd01.prod.outlook.com/ [2] https://lore.kernel.org/all/TY3PR01MB11346D2881A8CC9C3019C978386D22@TY3PR01MB11346.jpnprd01.prod.outlook.com Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds