* [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs
@ 2025-10-28 17:54 Prabhakar
2025-10-28 17:54 ` [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Prabhakar
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This series of patches adds support for Ethernet on the RZ/T2H (R9A09G077)
and RZ/N2H (R9A09G087) SoCs. It includes the addition of the MII Converter
(ETHSS) node, GMAC nodes, and enables Ethernet support in the
RZ/T2H-N2H-EVK board DTS.
v1->v2 changes:
- Dropped *skew-psec properties which are not needed for
VSC8541 PHYs.
v1: https://lore.kernel.org/all/20251016202129.157614-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (5):
arm64: dts: renesas: r9a09g077: Add ETHSS node
arm64: dts: renesas: r9a09g087: Add ETHSS node
arm64: dts: renesas: r9a09g077: Add GMAC nodes
arm64: dts: renesas: r9a09g087: Add GMAC nodes
arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 482 +++++++++++++++++
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 70 +++
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 485 ++++++++++++++++++
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 79 +++
.../dts/renesas/rzt2h-n2h-evk-common.dtsi | 70 +++
5 files changed, 1186 insertions(+)
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
@ 2025-10-28 17:54 ` Prabhakar
2025-11-10 14:50 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: " Prabhakar
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/T2H
(R9A09G077) SoC. The ETHSS IP block is responsible for handling MII
pass-through or conversion to RMII/RGMII.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2 changes:
- No changes.
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 2acca4bc1d3a..8a530c12a6dc 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -270,6 +270,43 @@ i2c2: i2c@81008000 {
status = "disabled";
};
+ ethss: ethss@80110000 {
+ compatible = "renesas,r9a09g077-miic";
+ reg = <0 0x80110000 0 0x10000>;
+ clocks = <&cpg CPG_CORE R9A09G077_ETCLKE>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>,
+ <&cpg CPG_CORE R9A09G077_ETCLKD>,
+ <&cpg CPG_MOD 403>;
+ clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+ resets = <&cpg 405>, <&cpg 406>;
+ reset-names = "rst", "crst";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mii_conv0: mii-conv@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ mii_conv1: mii-conv@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ mii_conv2: mii-conv@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mii_conv3: mii-conv@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g077-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: Add ETHSS node
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
2025-10-28 17:54 ` [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Prabhakar
@ 2025-10-28 17:54 ` Prabhakar
2025-11-10 14:51 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes Prabhakar
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H
(R9A09G087) SoC. The ETHSS IP block is responsible for handling MII
pass-through or conversion to RMII/RGMII.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2 changes:
- No changes.
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 3ece794fb0a7..fe0087a7d4b4 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -270,6 +270,43 @@ i2c2: i2c@81008000 {
status = "disabled";
};
+ ethss: ethss@80110000 {
+ compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
+ reg = <0 0x80110000 0 0x10000>;
+ clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>,
+ <&cpg CPG_CORE R9A09G087_ETCLKB>,
+ <&cpg CPG_CORE R9A09G087_ETCLKD>,
+ <&cpg CPG_MOD 403>;
+ clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+ resets = <&cpg 405>, <&cpg 406>;
+ reset-names = "rst", "crst";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mii_conv0: mii-conv@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ mii_conv1: mii-conv@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ mii_conv2: mii-conv@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mii_conv3: mii-conv@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+ };
+
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
2025-10-28 17:54 ` [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Prabhakar
2025-10-28 17:54 ` [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-10-28 17:54 ` Prabhakar
2025-11-10 14:53 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: " Prabhakar
2025-10-28 17:54 ` [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Prabhakar
4 siblings, 1 reply; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add Ethernet MAC (GMAC) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
The RZ/T2H integrates three GMAC interfaces based on the Synopsys
DesignWare MAC (version 5.20).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2 changes:
- No changes.
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 445 +++++++++++++++++++++
1 file changed, 445 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 8a530c12a6dc..f5fa6ca06409 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -270,6 +270,444 @@ i2c2: i2c@81008000 {
status = "disabled";
};
+ gmac0: ethernet@80100000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x80100000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 400>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 400>, <&cpg 401>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup0>;
+ snps,mtl-tx-config = <&mtl_tx_setup0>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup0: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup0: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac1: ethernet@92000000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x92000000 0 0x10000>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 416>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 416>, <&cpg 417>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac2: ethernet@92010000 {
+ compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
+ reg = <0 0x92010000 0 0x10000>;
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 417>,
+ <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G077_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 418>, <&cpg 419>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup2>;
+ snps,mtl-tx-config = <&mtl_tx_setup2>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio2: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup2: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup2: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
ethss: ethss@80110000 {
compatible = "renesas,r9a09g077-miic";
reg = <0 0x80110000 0 0x10000>;
@@ -495,6 +933,13 @@ sdhi1_vqmmc: vqmmc-regulator {
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: Add GMAC nodes
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
` (2 preceding siblings ...)
2025-10-28 17:54 ` [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes Prabhakar
@ 2025-10-28 17:54 ` Prabhakar
2025-11-10 14:54 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Prabhakar
4 siblings, 1 reply; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add Ethernet MAC (GMAC) device nodes to the RZ/N2H (R9A09G087) SoC DTSI.
The RZ/T2H integrates three GMAC interfaces based on the Synopsys
DesignWare MAC (version 5.20).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2 changes:
- No changes.
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 448 +++++++++++++++++++++
1 file changed, 448 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index fe0087a7d4b4..361a9235f00d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -270,6 +270,447 @@ i2c2: i2c@81008000 {
status = "disabled";
};
+ gmac0: ethernet@80100000 {
+ compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
+ "snps,dwmac-5.20";
+ reg = <0 0x80100000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 400>,
+ <&cpg CPG_CORE R9A09G087_CLK_PCLKH>,
+ <&cpg CPG_CORE R9A09G087_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 400>, <&cpg 401>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup0>;
+ snps,mtl-tx-config = <&mtl_tx_setup0>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup0: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup0: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac1: ethernet@92000000 {
+ compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
+ "snps,dwmac-5.20";
+ reg = <0 0x92000000 0 0x10000>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 416>,
+ <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G087_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 416>, <&cpg 417>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup1>;
+ snps,mtl-tx-config = <&mtl_tx_setup1>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup1: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup1: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac2: ethernet@92010000 {
+ compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth",
+ "snps,dwmac-5.20";
+ reg = <0 0x92010000 0 0x10000>;
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
+ "rx-queue-0", "rx-queue-1", "rx-queue-2",
+ "rx-queue-3", "rx-queue-4", "rx-queue-5",
+ "rx-queue-6", "rx-queue-7", "tx-queue-0",
+ "tx-queue-1", "tx-queue-2", "tx-queue-3",
+ "tx-queue-4", "tx-queue-5", "tx-queue-6",
+ "tx-queue-7";
+ clocks = <&cpg CPG_MOD 417>,
+ <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>,
+ <&cpg CPG_CORE R9A09G087_ETCLKB>;
+ clock-names = "stmmaceth", "pclk", "tx";
+ resets = <&cpg 418>, <&cpg 419>;
+ reset-names = "stmmaceth", "ahb";
+ power-domains = <&cpg>;
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <32>;
+ rx-fifo-depth = <8192>;
+ tx-fifo-depth = <8192>;
+ snps,fixed-burst;
+ snps,no-pbl-x8;
+ snps,force_thresh_dma_mode;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup2>;
+ snps,mtl-tx-config = <&mtl_tx_setup2>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ status = "disabled";
+
+ mdio2: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mtl_rx_setup2: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,map-to-dma-channel = <0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,map-to-dma-channel = <1>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x4>;
+ snps,map-to-dma-channel = <2>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x8>;
+ snps,map-to-dma-channel = <3>;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ snps,priority = <0x10>;
+ snps,map-to-dma-channel = <4>;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ snps,priority = <0x20>;
+ snps,map-to-dma-channel = <5>;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ snps,priority = <0x40>;
+ snps,map-to-dma-channel = <6>;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ snps,priority = <0x80>;
+ snps,map-to-dma-channel = <7>;
+ };
+ };
+
+ mtl_tx_setup2: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ };
+
+ queue4 {
+ snps,dcb-algorithm;
+ };
+
+ queue5 {
+ snps,dcb-algorithm;
+ };
+
+ queue6 {
+ snps,dcb-algorithm;
+ };
+
+ queue7 {
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
ethss: ethss@80110000 {
compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
reg = <0 0x80110000 0 0x10000>;
@@ -495,6 +936,13 @@ sdhi1_vqmmc: vqmmc-regulator {
};
};
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,lpi_en;
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <16 8 4 0 0 0 0>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
` (3 preceding siblings ...)
2025-10-28 17:54 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-10-28 17:54 ` Prabhakar
2025-11-10 16:16 ` Geert Uytterhoeven
4 siblings, 1 reply; 13+ messages in thread
From: Prabhakar @ 2025-10-28 17:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs.
Configure the MIIC converter in mode 0x6:
Port 0 <-> ETHSW Port 0
Port 1 <-> ETHSW Port 1
Port 2 <-> GMAC2
Port 3 <-> GMAC1
Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added
once the switch driver is available.
Configure the MIIC converters to map ports according to the selected
switching mode, with converters 0 and 1 mapped to switch ports and
converters 2 and 3 mapped to GMAC ports.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2 changes:
- Dropped *skew-psec properties which are not needed for
VSC8541 PHYs.
---
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 70 ++++++++++++++++
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 79 +++++++++++++++++++
.../dts/renesas/rzt2h-n2h-evk-common.dtsi | 70 ++++++++++++++++
3 files changed, 219 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 799c58afd6fe..33cbf74933de 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -149,7 +149,77 @@ &i2c1 {
status = "okay";
};
+&phy2 {
+ /*
+ * PHY2 Reset Configuration:
+ *
+ * SW6[1] = OFF; SW6[2] = ON; SW6[3] = OFF;
+ * P17_5 is used as GMAC_RESETOUT2#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
+};
+
+&phy3 {
+ reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
+};
+
&pinctrl {
+ /*
+ * ETH2 Pin Configuration:
+ *
+ * SW2[6] = OFF: MDC and MDIO of Ethernet port 2 are connected to GMAC2
+ * SW2[7] = ON: Pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 are used for Ethernet port 2
+ */
+ eth2_pins: eth2-pins {
+ pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+ <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
+ <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
+ <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
+ <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
+ <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+ <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+ <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
+ <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
+ <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
+ <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
+ <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+ <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+ <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
+ <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+ <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+ <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
+ <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
+ <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
+ };
+
+ /*
+ * ETH3 Pin Configuration:
+ *
+ * SW2[8] = ON, P27_2, P33_2-P33_7, P34_0-P34_5, P34_7 and P35_0-P35_5
+ * are used for Ethernet port 3
+ */
+ eth3_pins: eth3-pins {
+ pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+ <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
+ <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
+ <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
+ <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
+ <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+ <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+ <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
+ <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
+ <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
+ <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
+ <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+ <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
+ <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
+ <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
+ <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
+ <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
+ <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
+ <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
+ };
+
/*
* I2C0 Pin Configuration:
* ------------------------
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index d698b6368ee7..7ebc89bafaf1 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -186,7 +186,86 @@ &i2c1 {
status = "okay";
};
+&phy2 {
+ /*
+ * PHY2 Reset Configuration:
+ *
+ * DSW8[1] = ON; DSW8[2] = OFF
+ * DSW12[7] = OFF; DSW12[8] = ON
+ * P03_1 is used as GMAC_RESETOUT2#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
+};
+
+&phy3 {
+ /*
+ * PHY3 Reset Configuration:
+ *
+ * DSW12[5] = OFF; DSW12[6] = ON
+ * P03_2 is used as GMAC_RESETOUT3#
+ */
+ reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
+};
+
&pinctrl {
+ /*
+ * ETH2 Pin Configuration:
+ *
+ * DSW5[6] = OFF, P21_4-P21_5 are used for Ethernet port 2
+ * DSW5[7] = ON, P29_1-P29_7, P30_0-P30_4, P30_7, P31_2, P31_4
+ * and P31_5 are used for Ethernet port 2
+ */
+ eth2_pins: eth2-pins {
+ pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
+ <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
+ <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
+ <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
+ <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
+ <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
+ <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
+ <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
+ <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
+ <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
+ <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
+ <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
+ <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
+ <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
+ <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
+ <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
+ <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
+ <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
+ <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
+
+ };
+
+ /*
+ * ETH3 Pin Configuration:
+ *
+ * DSW5[8] = ON, P00_0-P00_2, P33_2-P33_7, P34_0-P34_6, are used for Ethernet port 3
+ * DSW12[1] = OFF;DSW12[2] = ON, P00_3 is used for Ethernet port 3
+ */
+ eth3_pins: eth3-pins {
+ pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
+ <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
+ <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
+ <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
+ <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
+ <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
+ <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
+ <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
+ <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
+ <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
+ <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
+ <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
+ <RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
+ <RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
+ <RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
+ <RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
+ <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
+ <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
+ <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
+ };
+
/*
* I2C0 Pin Configuration:
* ------------------------
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 924a38c6cb0f..c608d97586ff 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -7,10 +7,14 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/mscc-phy-vsc8531.h>
+#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
/ {
aliases {
+ ethernet0 = &gmac1;
+ ethernet1 = &gmac2;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhi0;
@@ -70,10 +74,34 @@ &ehci {
status = "okay";
};
+ðss {
+ status = "okay";
+
+ renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
+};
+
&extal_clk {
clock-frequency = <25000000>;
};
+&gmac1 {
+ pinctrl-0 = <ð3_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy3>;
+ phy-mode = "rgmii-id";
+ pcs-handle = <&mii_conv3>;
+ status = "okay";
+};
+
+&gmac2 {
+ pinctrl-0 = <ð2_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy2>;
+ phy-mode = "rgmii-id";
+ pcs-handle = <&mii_conv2>;
+ status = "okay";
+};
+
&hsusb {
dr_mode = "otg";
status = "okay";
@@ -87,6 +115,48 @@ eeprom: eeprom@50 {
};
};
+&mdio1 {
+ phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ reset-assert-us = <2000>;
+ reset-deassert-us = <15000>;
+ };
+};
+
+&mdio2 {
+ phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
+ vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
+ reset-assert-us = <2000>;
+ reset-deassert-us = <15000>;
+ };
+};
+
+&mii_conv0 {
+ renesas,miic-input = <ETHSS_ETHSW_PORT0>;
+ status = "okay";
+};
+
+&mii_conv1 {
+ renesas,miic-input = <ETHSS_ETHSW_PORT1>;
+ status = "okay";
+};
+
+&mii_conv2 {
+ renesas,miic-input = <ETHSS_GMAC2_PORT>;
+ status = "okay";
+};
+
+&mii_conv3 {
+ renesas,miic-input = <ETHSS_GMAC1_PORT>;
+ status = "okay";
+};
+
&ohci {
dr_mode = "otg";
status = "okay";
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node
2025-10-28 17:54 ` [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Prabhakar
@ 2025-11-10 14:50 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2025-11-10 14:50 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/T2H
> (R9A09G077) SoC. The ETHSS IP block is responsible for handling MII
> pass-through or conversion to RMII/RGMII.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: Add ETHSS node
2025-10-28 17:54 ` [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-11-10 14:51 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2025-11-10 14:51 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H
> (R9A09G087) SoC. The ETHSS IP block is responsible for handling MII
> pass-through or conversion to RMII/RGMII.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes
2025-10-28 17:54 ` [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes Prabhakar
@ 2025-11-10 14:53 ` Geert Uytterhoeven
2025-11-10 15:05 ` Lad, Prabhakar
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2025-11-10 14:53 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add Ethernet MAC (GMAC) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
> The RZ/T2H integrates three GMAC interfaces based on the Synopsys
> DesignWare MAC (version 5.20).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -495,6 +933,13 @@ sdhi1_vqmmc: vqmmc-regulator {
> };
> };
>
> + stmmac_axi_setup: stmmac-axi-config {
I will move this up while applying, to preserve sort order
(alphabetical).
> + snps,lpi_en;
> + snps,wr_osr_lmt = <0xf>;
> + snps,rd_osr_lmt = <0xf>;
> + snps,blen = <16 8 4 0 0 0 0>;
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.19, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: Add GMAC nodes
2025-10-28 17:54 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: " Prabhakar
@ 2025-11-10 14:54 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2025-11-10 14:54 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add Ethernet MAC (GMAC) device nodes to the RZ/N2H (R9A09G087) SoC DTSI.
> The RZ/T2H integrates three GMAC interfaces based on the Synopsys
RZ/N2H
> DesignWare MAC (version 5.20).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> @@ -495,6 +936,13 @@ sdhi1_vqmmc: vqmmc-regulator {
> };
> };
>
> + stmmac_axi_setup: stmmac-axi-config {
I will move this up while applying, to preserve sort order
(alphabetical).
> + snps,lpi_en;
> + snps,wr_osr_lmt = <0xf>;
> + snps,rd_osr_lmt = <0xf>;
> + snps,blen = <16 8 4 0 0 0 0>;
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.19, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes
2025-11-10 14:53 ` Geert Uytterhoeven
@ 2025-11-10 15:05 ` Lad, Prabhakar
0 siblings, 0 replies; 13+ messages in thread
From: Lad, Prabhakar @ 2025-11-10 15:05 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Nov 10, 2025 at 2:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add Ethernet MAC (GMAC) device nodes to the RZ/T2H (R9A09G077) SoC DTSI.
> > The RZ/T2H integrates three GMAC interfaces based on the Synopsys
> > DesignWare MAC (version 5.20).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
>
> > @@ -495,6 +933,13 @@ sdhi1_vqmmc: vqmmc-regulator {
> > };
> > };
> >
> > + stmmac_axi_setup: stmmac-axi-config {
>
> I will move this up while applying, to preserve sort order
> (alphabetical).
>
Oops. Thank you for taking care of it (and also for patch 4/5)
Cheers,
Prabhakar
> > + snps,lpi_en;
> > + snps,wr_osr_lmt = <0xf>;
> > + snps,rd_osr_lmt = <0xf>;
> > + snps,blen = <16 8 4 0 0 0 0>;
> > + };
> > +
> > timer {
> > compatible = "arm,armv8-timer";
> > interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-devel for v6.19, with the above fixed.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
2025-10-28 17:54 ` [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Prabhakar
@ 2025-11-10 16:16 ` Geert Uytterhoeven
2025-11-10 20:08 ` Lad, Prabhakar
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2025-11-10 16:16 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Prabhakar,
On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs.
>
> Configure the MIIC converter in mode 0x6:
> Port 0 <-> ETHSW Port 0
> Port 1 <-> ETHSW Port 1
> Port 2 <-> GMAC2
> Port 3 <-> GMAC1
>
> Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added
> once the switch driver is available.
>
> Configure the MIIC converters to map ports according to the selected
> switching mode, with converters 0 and 1 mapped to switch ports and
> converters 2 and 3 mapped to GMAC ports.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
I found the mapping between GMACx, ETHy, PHYz, and board connector
rather hard to follow. Some suggestions for improvement are included
below...
> --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> @@ -149,7 +149,77 @@ &i2c1 {
> status = "okay";
> };
>
> +&phy2 {
> + /*
> + * PHY2 Reset Configuration:
> + *
> + * SW6[1] = OFF; SW6[2] = ON; SW6[3] = OFF;
> + * P17_5 is used as GMAC_RESETOUT2#
> + */
> + reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
> +};
> +
> +&phy3 {
> + reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
> +};
> +
> &pinctrl {
> + /*
> + * ETH2 Pin Configuration:
> + *
> + * SW2[6] = OFF: MDC and MDIO of Ethernet port 2 are connected to GMAC2
> + * SW2[7] = ON: Pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 are used for Ethernet port 2
Please split this long line.
> + */
> + eth2_pins: eth2-pins {
Perhaps s/eth2/gmac2/, to make the mapping easier to follow?
> + pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
> + <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
> + <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
> + <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
> + <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
The documentation doesn't use square brackets in the signal names.
> + <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
> + <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
> + <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
> + <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
> + <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
> + <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
> + <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
> + <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
> + <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
> + <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
> + <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
> + <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
> + <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
The documentation calls these GMAC2_{MDC,MDIO}.
> + <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
Please settle on a common convention for formatting pinmux settings:
either use 0x2 here (no leading zero), or 0x0f in the other entries.
> + };
> +
> + /*
> + * ETH3 Pin Configuration:
> + *
> + * SW2[8] = ON, P27_2, P33_2-P33_7, P34_0-P34_5, P34_7 and P35_0-P35_5
P27_2 and P35_3-P35_5 don't seem to be muxed by SW2[8]?
> + * are used for Ethernet port 3
> + */
> + eth3_pins: eth3-pins {
> + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
> + <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
> + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
> + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
> + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
> + <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
> + <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
> + <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
> + <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
> + <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
> + <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
> + <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
> + <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
> + <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
> + <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
> + <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
> + <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
> + <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
> + <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
> + };
> +
> /*
> * I2C0 Pin Configuration:
> * ------------------------
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> index d698b6368ee7..7ebc89bafaf1 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> @@ -186,7 +186,86 @@ &i2c1 {
> status = "okay";
> };
>
> +&phy2 {
> + /*
> + * PHY2 Reset Configuration:
> + *
> + * DSW8[1] = ON; DSW8[2] = OFF
> + * DSW12[7] = OFF; DSW12[8] = ON
> + * P03_1 is used as GMAC_RESETOUT2#
> + */
> + reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
> +};
> +
> +&phy3 {
> + /*
> + * PHY3 Reset Configuration:
> + *
> + * DSW12[5] = OFF; DSW12[6] = ON
> + * P03_2 is used as GMAC_RESETOUT3#
> + */
> + reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
> +};
> +
> &pinctrl {
> + /*
> + * ETH2 Pin Configuration:
> + *
> + * DSW5[6] = OFF, P21_4-P21_5 are used for Ethernet port 2
MDC and MDIO of Ethernet port 2 are connected to GMAC2
> + * DSW5[7] = ON, P29_1-P29_7, P30_0-P30_4, P30_7, P31_2, P31_4
> + * and P31_5 are used for Ethernet port 2
> + */
> + eth2_pins: eth2-pins {
Perhaps s/eth2/gmac2/, to make the mapping easier to follow?
> + pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
> + <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
> + <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
> + <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
> + <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
> + <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
> + <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
> + <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
> + <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
> + <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
> + <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
> + <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
> + <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
> + <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
31, 1, 0xf
> + <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
> + <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
> + <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
> + <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
The documentation calls these GMAC2_{MDC,MDIO}.
> + <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
> +
> + };
> +
> + /*
> + * ETH3 Pin Configuration:
> + *
> + * DSW5[8] = ON, P00_0-P00_2, P33_2-P33_7, P34_0-P34_6, are used for Ethernet port 3
> + * DSW12[1] = OFF;DSW12[2] = ON, P00_3 is used for Ethernet port 3
> + */
> + eth3_pins: eth3-pins {
Perhaps s/eth3/gmac1/, to make the mapping easier to follow?
> + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
> + <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
> + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
> + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
> + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
> + <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
> + <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
> + <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
> + <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
> + <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
> + <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
> + <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
> + <RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
> + <RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
> + <RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
> + <RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
> + <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
> + <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
The documentation calls these GMAC1_{MDC,MDIO}.
> + <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
> + };
> +
> /*
> * I2C0 Pin Configuration:
> * ------------------------
> diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> index 924a38c6cb0f..c608d97586ff 100644
> --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> @@ -7,10 +7,14 @@
>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/leds/common.h>
> +#include <dt-bindings/net/mscc-phy-vsc8531.h>
> +#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
> #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
>
> / {
> aliases {
> + ethernet0 = &gmac1;
Is this the port labeled "Ethernet(ETH3) Connector" in the Board's
User Manual? Shouldn't that be "ethernet3"?
> + ethernet1 = &gmac2;
Is this the port labeled "Ethernet(ETH2) Connector" in the Board's
User Manual? Shouldn't that be "ethernet2"?
> i2c0 = &i2c0;
> i2c1 = &i2c1;
> mmc0 = &sdhi0;
> @@ -70,10 +74,34 @@ &ehci {
> status = "okay";
> };
>
> +ðss {
> + status = "okay";
> +
> + renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
> +};
> +
> &extal_clk {
> clock-frequency = <25000000>;
> };
>
> +&gmac1 {
> + pinctrl-0 = <ð3_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&phy3>;
> + phy-mode = "rgmii-id";
> + pcs-handle = <&mii_conv3>;
> + status = "okay";
> +};
> +
> +&gmac2 {
> + pinctrl-0 = <ð2_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&phy2>;
> + phy-mode = "rgmii-id";
> + pcs-handle = <&mii_conv2>;
> + status = "okay";
> +};
> +
> &hsusb {
> dr_mode = "otg";
> status = "okay";
> @@ -87,6 +115,48 @@ eeprom: eeprom@50 {
> };
> };
>
> +&mdio1 {
> + phy3: ethernet-phy@3 {
Ah, the "3" corresponds to the PHY address in this mdio node...
Perhaps "mdio1_phy", to make it easier to match mdio and phy nodes?
> + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
> + reg = <3>;
> + vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
VSC8531_ACTIVITY?
> + vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
> + reset-assert-us = <2000>;
> + reset-deassert-us = <15000>;
> + };
> +};
> +
> +&mdio2 {
> + phy2: ethernet-phy@2 {
mdio2_phy?
> + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
> + reg = <2>;
> + vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
VSC8531_ACTIVITY?
> + vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
> + reset-assert-us = <2000>;
> + reset-deassert-us = <15000>;
> + };
> +};
> +
> +&mii_conv0 {
> + renesas,miic-input = <ETHSS_ETHSW_PORT0>;
> + status = "okay";
> +};
> +
> +&mii_conv1 {
> + renesas,miic-input = <ETHSS_ETHSW_PORT1>;
> + status = "okay";
> +};
> +
> +&mii_conv2 {
> + renesas,miic-input = <ETHSS_GMAC2_PORT>;
> + status = "okay";
> +};
> +
> +&mii_conv3 {
> + renesas,miic-input = <ETHSS_GMAC1_PORT>;
> + status = "okay";
> +};
> +
> &ohci {
> dr_mode = "otg";
> status = "okay";
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support
2025-11-10 16:16 ` Geert Uytterhoeven
@ 2025-11-10 20:08 ` Lad, Prabhakar
0 siblings, 0 replies; 13+ messages in thread
From: Lad, Prabhakar @ 2025-11-10 20:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc, devicetree, linux-kernel, Biju Das,
Fabrizio Castro, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Nov 10, 2025 at 4:16 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 28 Oct 2025 at 18:55, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable Ethernet support on the RZ/T2H and RZ/N2H EVKs.
> >
> > Configure the MIIC converter in mode 0x6:
> > Port 0 <-> ETHSW Port 0
> > Port 1 <-> ETHSW Port 1
> > Port 2 <-> GMAC2
> > Port 3 <-> GMAC1
> >
> > Enable the ETHSS, GMAC1 and GMAC2 nodes. ETHSW support will be added
> > once the switch driver is available.
> >
> > Configure the MIIC converters to map ports according to the selected
> > switching mode, with converters 0 and 1 mapped to switch ports and
> > converters 2 and 3 mapped to GMAC ports.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> I found the mapping between GMACx, ETHy, PHYz, and board connector
> rather hard to follow. Some suggestions for improvement are included
> below...
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > @@ -149,7 +149,77 @@ &i2c1 {
> > status = "okay";
> > };
> >
> > +&phy2 {
> > + /*
> > + * PHY2 Reset Configuration:
> > + *
> > + * SW6[1] = OFF; SW6[2] = ON; SW6[3] = OFF;
> > + * P17_5 is used as GMAC_RESETOUT2#
> > + */
> > + reset-gpios = <&pinctrl RZT2H_GPIO(17, 5) GPIO_ACTIVE_LOW>;
> > +};
> > +
> > +&phy3 {
> > + reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>;
> > +};
> > +
> > &pinctrl {
> > + /*
> > + * ETH2 Pin Configuration:
> > + *
> > + * SW2[6] = OFF: MDC and MDIO of Ethernet port 2 are connected to GMAC2
> > + * SW2[7] = ON: Pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 are used for Ethernet port 2
>
> Please split this long line.
>
Ok, I will split it up.
> > + */
> > + eth2_pins: eth2-pins {
>
> Perhaps s/eth2/gmac2/, to make the mapping easier to follow?
>
Agreed.
> > + pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
> > + <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
> > + <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
> > + <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
> > + <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
>
> The documentation doesn't use square brackets in the signal names.
>
Ok I will drop the square brackets.
> > + <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
> > + <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
> > + <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
> > + <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
> > + <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
> > + <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
> > + <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
> > + <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
> > + <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
> > + <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
> > + <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
> > + <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
> > + <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
>
> The documentation calls these GMAC2_{MDC,MDIO}.
>
Agreed, I will rename them.
> > + <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
>
> Please settle on a common convention for formatting pinmux settings:
> either use 0x2 here (no leading zero), or 0x0f in the other entries.
>
Ok, I will drop the leading zero.
> > + };
> > +
> > + /*
> > + * ETH3 Pin Configuration:
> > + *
> > + * SW2[8] = ON, P27_2, P33_2-P33_7, P34_0-P34_5, P34_7 and P35_0-P35_5
>
> P27_2 and P35_3-P35_5 don't seem to be muxed by SW2[8]?
>
Agreed, I will drop them (the EVK user manual had it).
> > + * are used for Ethernet port 3
> > + */
> > + eth3_pins: eth3-pins {
> > + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
> > + <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
> > + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
> > + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
> > + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
> > + <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
> > + <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
> > + <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
> > + <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
> > + <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
> > + <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
> > + <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
> > + <RZT2H_PORT_PINMUX(34, 7, 0xf)>, /* ETH3_TXER */
> > + <RZT2H_PORT_PINMUX(35, 0, 0xf)>, /* ETH3_RXER */
> > + <RZT2H_PORT_PINMUX(35, 1, 0xf)>, /* ETH3_CRS */
> > + <RZT2H_PORT_PINMUX(35, 2, 0xf)>, /* ETH3_COL */
> > + <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
> > + <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
> > + <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
> > + };
> > +
> > /*
> > * I2C0 Pin Configuration:
> > * ------------------------
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > index d698b6368ee7..7ebc89bafaf1 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > @@ -186,7 +186,86 @@ &i2c1 {
> > status = "okay";
> > };
> >
> > +&phy2 {
> > + /*
> > + * PHY2 Reset Configuration:
> > + *
> > + * DSW8[1] = ON; DSW8[2] = OFF
> > + * DSW12[7] = OFF; DSW12[8] = ON
> > + * P03_1 is used as GMAC_RESETOUT2#
> > + */
> > + reset-gpios = <&pinctrl RZT2H_GPIO(3, 1) GPIO_ACTIVE_LOW>;
> > +};
> > +
> > +&phy3 {
> > + /*
> > + * PHY3 Reset Configuration:
> > + *
> > + * DSW12[5] = OFF; DSW12[6] = ON
> > + * P03_2 is used as GMAC_RESETOUT3#
> > + */
> > + reset-gpios = <&pinctrl RZT2H_GPIO(3, 2) GPIO_ACTIVE_LOW>;
> > +};
> > +
> > &pinctrl {
> > + /*
> > + * ETH2 Pin Configuration:
> > + *
> > + * DSW5[6] = OFF, P21_4-P21_5 are used for Ethernet port 2
>
> MDC and MDIO of Ethernet port 2 are connected to GMAC2
>
Ok, I will update it to `DSW5[6] OFF - connect MDC/MDIO of Ethernet
port 2 to GMAC2`.
> > + * DSW5[7] = ON, P29_1-P29_7, P30_0-P30_4, P30_7, P31_2, P31_4
> > + * and P31_5 are used for Ethernet port 2
> > + */
> > + eth2_pins: eth2-pins {
>
> Perhaps s/eth2/gmac2/, to make the mapping easier to follow?
>
Agreed.
> > + pinmux = <RZT2H_PORT_PINMUX(29, 1, 0xf)>, /* ETH2_TXCLK */
> > + <RZT2H_PORT_PINMUX(29, 2, 0xf)>, /* ETH2_TXD[0] */
> > + <RZT2H_PORT_PINMUX(29, 3, 0xf)>, /* ETH2_TXD[1] */
> > + <RZT2H_PORT_PINMUX(29, 4, 0xf)>, /* ETH2_TXD[2] */
> > + <RZT2H_PORT_PINMUX(29, 5, 0xf)>, /* ETH2_TXD[3] */
> > + <RZT2H_PORT_PINMUX(29, 6, 0xf)>, /* ETH2_TXEN */
> > + <RZT2H_PORT_PINMUX(29, 7, 0xf)>, /* ETH2_RXCLK */
> > + <RZT2H_PORT_PINMUX(30, 0, 0xf)>, /* ETH2_RXD[0] */
> > + <RZT2H_PORT_PINMUX(30, 1, 0xf)>, /* ETH2_RXD[1] */
> > + <RZT2H_PORT_PINMUX(30, 2, 0xf)>, /* ETH2_RXD[2] */
> > + <RZT2H_PORT_PINMUX(30, 3, 0xf)>, /* ETH2_RXD[3] */
> > + <RZT2H_PORT_PINMUX(30, 4, 0xf)>, /* ETH2_RXDV */
> > + <RZT2H_PORT_PINMUX(31, 2, 0xf)>, /* ETH2_TXER */
> > + <RZT2H_PORT_PINMUX(31, 3, 0xf)>, /* ETH2_RXER */
>
> 31, 1, 0xf
>
Agreed.
> > + <RZT2H_PORT_PINMUX(31, 4, 0xf)>, /* ETH2_CRS */
> > + <RZT2H_PORT_PINMUX(31, 5, 0xf)>, /* ETH2_COL */
> > + <RZT2H_PORT_PINMUX(30, 5, 0x10)>, /* ETH2_MDC */
> > + <RZT2H_PORT_PINMUX(30, 6, 0x10)>, /* ETH2_MDIO */
>
> The documentation calls these GMAC2_{MDC,MDIO}.
>
Agreed, I will switch to using GMACX_*.
> > + <RZT2H_PORT_PINMUX(31, 0, 0x02)>; /* ETH2_REFCLK */
>
> > +
> > + };
> > +
> > + /*
> > + * ETH3 Pin Configuration:
> > + *
> > + * DSW5[8] = ON, P00_0-P00_2, P33_2-P33_7, P34_0-P34_6, are used for Ethernet port 3
> > + * DSW12[1] = OFF;DSW12[2] = ON, P00_3 is used for Ethernet port 3
> > + */
> > + eth3_pins: eth3-pins {
>
> Perhaps s/eth3/gmac1/, to make the mapping easier to follow?
>
Agreed.
> > + pinmux = <RZT2H_PORT_PINMUX(33, 2, 0xf)>, /* ETH3_TXCLK */
> > + <RZT2H_PORT_PINMUX(33, 3, 0xf)>, /* ETH3_TXD[0] */
> > + <RZT2H_PORT_PINMUX(33, 4, 0xf)>, /* ETH3_TXD[1] */
> > + <RZT2H_PORT_PINMUX(33, 5, 0xf)>, /* ETH3_TXD[2] */
> > + <RZT2H_PORT_PINMUX(33, 6, 0xf)>, /* ETH3_TXD[3] */
> > + <RZT2H_PORT_PINMUX(33, 7, 0xf)>, /* ETH3_TXEN */
> > + <RZT2H_PORT_PINMUX(34, 0, 0xf)>, /* ETH3_RXCLK */
> > + <RZT2H_PORT_PINMUX(34, 1, 0xf)>, /* ETH3_RXD[0] */
> > + <RZT2H_PORT_PINMUX(34, 2, 0xf)>, /* ETH3_RXD[1] */
> > + <RZT2H_PORT_PINMUX(34, 3, 0xf)>, /* ETH3_RXD[2] */
> > + <RZT2H_PORT_PINMUX(34, 4, 0xf)>, /* ETH3_RXD[3] */
> > + <RZT2H_PORT_PINMUX(34, 5, 0xf)>, /* ETH3_RXDV */
> > + <RZT2H_PORT_PINMUX(0, 0, 0xf)>, /* ETH3_TXER */
> > + <RZT2H_PORT_PINMUX(0, 1, 0xf)>, /* ETH3_RXER */
> > + <RZT2H_PORT_PINMUX(0, 2, 0xf)>, /* ETH3_CRS */
> > + <RZT2H_PORT_PINMUX(0, 3, 0xf)>, /* ETH3_COL */
> > + <RZT2H_PORT_PINMUX(26, 1, 0x10)>, /* ETH3_MDC */
> > + <RZT2H_PORT_PINMUX(26, 2, 0x10)>, /* ETH3_MDIO */
>
> The documentation calls these GMAC1_{MDC,MDIO}.
>
Agreed.
> > + <RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* ETH3_REFCLK */
> > + };
> > +
> > /*
> > * I2C0 Pin Configuration:
> > * ------------------------
> > diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > index 924a38c6cb0f..c608d97586ff 100644
> > --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
> > @@ -7,10 +7,14 @@
> >
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/net/mscc-phy-vsc8531.h>
> > +#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
> > #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> >
> > / {
> > aliases {
> > + ethernet0 = &gmac1;
>
> Is this the port labeled "Ethernet(ETH3) Connector" in the Board's
> User Manual? Shouldn't that be "ethernet3"?
>
Yes this is labeled as ETH3, so I will update it to "ethernet3".
> > + ethernet1 = &gmac2;
>
> Is this the port labeled "Ethernet(ETH2) Connector" in the Board's
> User Manual? Shouldn't that be "ethernet2"?
>
Yes this is labeled as ETH2, so I will update it to "ethernet2".
> > i2c0 = &i2c0;
> > i2c1 = &i2c1;
> > mmc0 = &sdhi0;
> > @@ -70,10 +74,34 @@ &ehci {
> > status = "okay";
> > };
> >
> > +ðss {
> > + status = "okay";
> > +
> > + renesas,miic-switch-portin = <ETHSS_GMAC0_PORT>;
> > +};
> > +
> > &extal_clk {
> > clock-frequency = <25000000>;
> > };
> >
> > +&gmac1 {
> > + pinctrl-0 = <ð3_pins>;
> > + pinctrl-names = "default";
> > + phy-handle = <&phy3>;
> > + phy-mode = "rgmii-id";
> > + pcs-handle = <&mii_conv3>;
> > + status = "okay";
> > +};
> > +
> > +&gmac2 {
> > + pinctrl-0 = <ð2_pins>;
> > + pinctrl-names = "default";
> > + phy-handle = <&phy2>;
> > + phy-mode = "rgmii-id";
> > + pcs-handle = <&mii_conv2>;
> > + status = "okay";
> > +};
> > +
> > &hsusb {
> > dr_mode = "otg";
> > status = "okay";
> > @@ -87,6 +115,48 @@ eeprom: eeprom@50 {
> > };
> > };
> >
> > +&mdio1 {
> > + phy3: ethernet-phy@3 {
>
> Ah, the "3" corresponds to the PHY address in this mdio node...
> Perhaps "mdio1_phy", to make it easier to match mdio and phy nodes?
>
Ok, I will use "mdio1_phy" for clarity.
> > + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
> > + reg = <3>;
> > + vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
>
> VSC8531_ACTIVITY?
>
Agreed.
> > + vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
> > + reset-assert-us = <2000>;
> > + reset-deassert-us = <15000>;
> > + };
> > +};
> > +
> > +&mdio2 {
> > + phy2: ethernet-phy@2 {
>
> mdio2_phy?
>
OK.
> > + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22";
> > + reg = <2>;
> > + vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
>
> VSC8531_ACTIVITY?
>
OK.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-11-10 20:09 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-28 17:54 [PATCH v2 0/5] Enable Ethernet support for RZ/T2H and RZ/N2H SoCs Prabhakar
2025-10-28 17:54 ` [PATCH v2 1/5] arm64: dts: renesas: r9a09g077: Add ETHSS node Prabhakar
2025-11-10 14:50 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 2/5] arm64: dts: renesas: r9a09g087: " Prabhakar
2025-11-10 14:51 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 3/5] arm64: dts: renesas: r9a09g077: Add GMAC nodes Prabhakar
2025-11-10 14:53 ` Geert Uytterhoeven
2025-11-10 15:05 ` Lad, Prabhakar
2025-10-28 17:54 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g087: " Prabhakar
2025-11-10 14:54 ` Geert Uytterhoeven
2025-10-28 17:54 ` [PATCH v2 5/5] arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support Prabhakar
2025-11-10 16:16 ` Geert Uytterhoeven
2025-11-10 20:08 ` Lad, Prabhakar
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