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[209.85.219.174]) by smtp.gmail.com with ESMTPSA id cm11-20020a05622a250b00b002f39b99f66fsm7505297qtb.9.2022.05.09.01.57.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 May 2022 01:57:13 -0700 (PDT) Received: by mail-yb1-f174.google.com with SMTP id m128so23647360ybm.5; Mon, 09 May 2022 01:57:12 -0700 (PDT) X-Received: by 2002:a25:4506:0:b0:648:cfc2:301d with SMTP id s6-20020a254506000000b00648cfc2301dmr12216717yba.380.1652086632606; Mon, 09 May 2022 01:57:12 -0700 (PDT) MIME-Version: 1.0 References: <20220509050953.11005-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220509050953.11005-2-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220509050953.11005-2-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Mon, 9 May 2022 10:57:00 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller To: Lad Prabhakar Cc: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Geert Uytterhoeven , Philipp Zabel , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Prabhakar , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Prabhakar, On Mon, May 9, 2022 at 7:10 AM Lad Prabhakar wrote: > Add DT bindings for the Renesas RZ/G2L Interrupt Controller. > > Signed-off-by: Lad Prabhakar > Reviewed-by: Rob Herring Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml > @@ -0,0 +1,131 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) > + > +maintainers: > + - Lad Prabhakar > + - Geert Uytterhoeven > + > +description: | > + IA55 performs various interrupt controls including synchronization for the external > + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral > + interrupts output by each IP. And it notifies the interrupt to the GIC > + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts > + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts > + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and > + stand-up edge detection interrupts) > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-irqc # RZ/G2L > + - const: renesas,rzg2l-irqc > + > + '#interrupt-cells': > + const: 2 Please document the meaning of the cells. The rest LGTM, so Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds