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[209.85.219.180]) by smtp.gmail.com with ESMTPSA id 78-20020a370551000000b0067e3a58c090sm1158291qkf.82.2022.04.01.05.02.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 01 Apr 2022 05:02:07 -0700 (PDT) Received: by mail-yb1-f180.google.com with SMTP id v35so4556585ybi.10; Fri, 01 Apr 2022 05:02:07 -0700 (PDT) X-Received: by 2002:a25:45:0:b0:633:96e2:2179 with SMTP id 66-20020a250045000000b0063396e22179mr8451190yba.393.1648814527141; Fri, 01 Apr 2022 05:02:07 -0700 (PDT) MIME-Version: 1.0 References: <20220315155919.23451-1-biju.das.jz@bp.renesas.com> <20220315155919.23451-8-biju.das.jz@bp.renesas.com> In-Reply-To: <20220315155919.23451-8-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Fri, 1 Apr 2022 14:01:55 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 7/7] arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform To: Biju Das Cc: Rob Herring , Magnus Damm , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Chris Paterson , Biju Das , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Biju, On Tue, Mar 15, 2022 at 4:59 PM Biju Das wrote: > Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. > > Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 > device selection is based on the SW1[3] switch position. > > Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. > Set SW1[3] to position ON for selecting Ethernet0. > > This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. > > Signed-off-by: Biju Das > Reviewed-by: Lad Prabhakar Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > @@ -52,11 +57,101 @@ > #endif > }; > > +#if (!SW_ET0_EN_N) > +ð0 { > + pinctrl-0 = <ð0_pins>; > + pinctrl-names = "default"; > + phy-handle = <&phy0>; > + phy-mode = "rgmii-id"; > + status = "okay"; > + > + phy0: ethernet-phy@7 { > + compatible = "ethernet-phy-id0022.1640", > + "ethernet-phy-ieee802.3-c22"; To be augmented with interrupt properties when the RZ/G2L IRQC driver and bindings have been completed. But that can be done later.. > + reg = <7>; > + rxc-skew-psec = <2400>; > + txc-skew-psec = <2400>; > + rxdv-skew-psec = <0>; > + txdv-skew-psec = <0>; > + rxd0-skew-psec = <0>; > + rxd1-skew-psec = <0>; > + rxd2-skew-psec = <0>; > + rxd3-skew-psec = <0>; > + txd0-skew-psec = <0>; > + txd1-skew-psec = <0>; > + txd2-skew-psec = <0>; > + txd3-skew-psec = <0>; > + }; > +}; > +#endif > + > +ð1 { > + pinctrl-0 = <ð1_pins>; > + pinctrl-names = "default"; > + phy-handle = <&phy1>; > + phy-mode = "rgmii-id"; > + status = "okay"; > + > + phy1: ethernet-phy@7 { > + compatible = "ethernet-phy-id0022.1640", > + "ethernet-phy-ieee802.3-c22"; > + reg = <7>; Likewise. > + rxc-skew-psec = <2400>; > + txc-skew-psec = <2400>; > + rxdv-skew-psec = <0>; > + txdv-skew-psec = <0>; > + rxd0-skew-psec = <0>; > + rxd1-skew-psec = <0>; > + rxd2-skew-psec = <0>; > + rxd3-skew-psec = <0>; > + txd0-skew-psec = <0>; > + txd1-skew-psec = <0>; > + txd2-skew-psec = <0>; > + txd3-skew-psec = <0>; > + }; > +}; Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds