[PATCH 0/4] arm64: dts: renesas: Add XSPI support for RZ/V2N and RZ/V2H(P) SoCs and EVK

[PATCH 0/4] arm64: dts: renesas: Add XSPI support for RZ/V2N and RZ/V2H(P) SoCs and EVK

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi all,

This patch series adds XSPI support to the Renesas RZ/V2N (R9A09G056)
and RZ/V2H(P) (R9A09G057) SoCs. It introduces the XSPI controller nodes
in the SoC-level DTSI files and enables a connected serial NOR flash
device on the respective evaluation boards.

Note,
- DT binding patches have been posted seprately [0]
- Clock support has been posted already [1] to ML
- Patches apply on top of series [2]

[0] https://lore.kernel.org/all/20250624171605.469724-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://lore.kernel.org/all/20250624173030.472196-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://lore.kernel.org/all/20250620121045.56114-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (4):
  arm64: dts: renesas: r9a09g056: Add XSPI node
  arm64: dts: renesas: r9a09g057: Add XSPI node
  arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH

 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 23 +++++++++
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 48 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 23 +++++++++
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    | 48 +++++++++++++++++++
 4 files changed, 142 insertions(+)

-- 
2.49.0

[PATCH 1/4] arm64: dts: renesas: r9a09g056: Add XSPI node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 617b9ec9eef1..68585ece796e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -208,6 +208,29 @@ sys: system-controller@10430000 {
 			resets = <&cpg 0x30>;
 		};
 
+		xspi: spi@11030000 {
+			compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x11030000 0 0x10000>,
+			      <0 0x20000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 0x9f>,
+				 <&cpg CPG_MOD 0xa0>,
+				 <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
+				 <&cpg CPG_MOD 0xa1>;
+			clock-names = "ahb", "axi", "spi", "spix2";
+			assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
+			assigned-clock-rates = <133333334>;
+			resets = <&cpg 0xa3>, <&cpg 0xa4>;
+			reset-names = "hresetn", "aresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		ostm0: timer@11800000 {
 			compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
 			reg = <0x0 0x11800000 0x0 0x1000>;
-- 
2.49.0

[PATCH 2/4] arm64: dts: renesas: r9a09g057: Add XSPI node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add XSPI node to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 45aedd62a259..258744468079 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -280,6 +280,29 @@ sys: system-controller@10430000 {
 			resets = <&cpg 0x30>;
 		};
 
+		xspi: spi@11030000 {
+			compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
+			reg = <0 0x11030000 0 0x10000>,
+			      <0 0x20000000 0 0x10000000>;
+			reg-names = "regs", "dirmap";
+			interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "pulse", "err_pulse";
+			clocks = <&cpg CPG_MOD 0x9f>,
+				 <&cpg CPG_MOD 0xa0>,
+				 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
+				 <&cpg CPG_MOD 0xa1>;
+			clock-names = "ahb", "axi", "spi", "spix2";
+			assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
+			assigned-clock-rates = <133333334>;
+			resets = <&cpg 0xa3>, <&cpg 0xa4>;
+			reset-names = "hresetn", "aresetn";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller@11400000 {
 			compatible = "renesas,r9a09g057-dmac";
 			reg = <0 0x11400000 0 0x10000>;
-- 
2.49.0

[PATCH 3/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable MT25QU512ABB8E12 FLASH connected to XSPI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
index 5c4ee66b12ee..73e95425c89a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
@@ -342,6 +342,18 @@ vbus {
 			pinmux = <RZV2N_PORT_PINMUX(9, 5, 14)>; /* VBUS */
 		};
 	};
+
+	xspi_pins: xspi0 {
+		ctrl {
+			pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
+			output-enable;
+		};
+
+		io {
+			pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
+			renesas,output-impedance = <3>;
+		};
+	};
 };
 
 &qextal_clk {
@@ -384,3 +396,39 @@ &usb2_phy0 {
 &wdt1 {
 	status = "okay";
 };
+
+&xspi {
+	pinctrl-0 = <&xspi_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		vcc-supply = <&reg_1p8v>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000000 0x00060000>;
+			};
+
+			partition@60000 {
+				label = "fip";
+				reg = <0x00060000 0x1fa0000>;
+			};
+
+			partition@2000000 {
+				label = "user";
+				reg = <0x2000000 0x2000000>;
+			};
+		};
+	};
+};
-- 
2.49.0

[PATCH 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable MT25QU512ABB8E12 FLASH connected to XSPI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index f9a0e9aefe7a..1af03cb143ba 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -371,6 +371,18 @@ vbus {
 			pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */
 		};
 	};
+
+	xspi_pins: xspi0 {
+		ctrl {
+			pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
+			output-enable;
+		};
+
+		io {
+			pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
+			renesas,output-impedance = <3>;
+		};
+	};
 };
 
 &qextal_clk {
@@ -425,3 +437,39 @@ &usb2_phy1 {
 &wdt1 {
 	status = "okay";
 };
+
+&xspi {
+	pinctrl-0 = <&xspi_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		vcc-supply = <&reg_1p8v>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000000 0x00060000>;
+			};
+
+			partition@60000 {
+				label = "fip";
+				reg = <0x00060000 0x1fa0000>;
+			};
+
+			partition@2000000 {
+				label = "user";
+				reg = <0x2000000 0x2000000>;
+			};
+		};
+	};
+};
-- 
2.49.0

Re: [PATCH 1/4] arm64: dts: renesas: r9a09g056: Add XSPI node

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> @@ -208,6 +208,29 @@ sys: system-controller@10430000 {
>                         resets = <&cpg 0x30>;
>                 };
>
> +               xspi: spi@11030000 {
> +                       compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
> +                       reg = <0 0x11030000 0 0x10000>,
> +                             <0 0x20000000 0 0x10000000>;
> +                       reg-names = "regs", "dirmap";
> +                       interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "pulse", "err_pulse";
> +                       clocks = <&cpg CPG_MOD 0x9f>,
> +                                <&cpg CPG_MOD 0xa0>,
> +                                <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
> +                                <&cpg CPG_MOD 0xa1>;
> +                       clock-names = "ahb", "axi", "spi", "spix2";
> +                       assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
> +                       assigned-clock-rates = <133333334>;

Do you need these two properties?
If yes, perhaps they should be moved to the board part?

> +                       resets = <&cpg 0xa3>, <&cpg 0xa4>;
> +                       reset-names = "hresetn", "aresetn";
> +                       power-domains = <&cpg>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
>                 ostm0: timer@11800000 {
>                         compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
>                         reg = <0x0 0x11800000 0x0 0x1000>;

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] arm64: dts: renesas: r9a09g057: Add XSPI node

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add XSPI node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -280,6 +280,29 @@ sys: system-controller@10430000 {
>                         resets = <&cpg 0x30>;
>                 };
>
> +               xspi: spi@11030000 {
> +                       compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
> +                       reg = <0 0x11030000 0 0x10000>,
> +                             <0 0x20000000 0 0x10000000>;
> +                       reg-names = "regs", "dirmap";
> +                       interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> +                       interrupt-names = "pulse", "err_pulse";
> +                       clocks = <&cpg CPG_MOD 0x9f>,
> +                                <&cpg CPG_MOD 0xa0>,
> +                                <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
> +                                <&cpg CPG_MOD 0xa1>;
> +                       clock-names = "ahb", "axi", "spi", "spix2";
> +                       assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
> +                       assigned-clock-rates = <133333334>;

Same question as [PATCH 1/4].

> +                       resets = <&cpg 0xa3>, <&cpg 0xa4>;
> +                       reset-names = "hresetn", "aresetn";
> +                       power-domains = <&cpg>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";
> +               };
> +
>                 dmac0: dma-controller@11400000 {
>                         compatible = "renesas,r9a09g057-dmac";
>                         reg = <0 0x11400000 0 0x10000>;

The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH

[Geert Uytterhoeven]

On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable MT25QU512ABB8E12 FLASH connected to XSPI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH

[Geert Uytterhoeven]

On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable MT25QU512ABB8E12 FLASH connected to XSPI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] arm64: dts: renesas: r9a09g056: Add XSPI node

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Jul 1, 2025 at 1:07 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add XSPI node to RZ/V2N ("R9A09G056") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> > @@ -208,6 +208,29 @@ sys: system-controller@10430000 {
> >                         resets = <&cpg 0x30>;
> >                 };
> >
> > +               xspi: spi@11030000 {
> > +                       compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi";
> > +                       reg = <0 0x11030000 0 0x10000>,
> > +                             <0 0x20000000 0 0x10000000>;
> > +                       reg-names = "regs", "dirmap";
> > +                       interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > +                       interrupt-names = "pulse", "err_pulse";
> > +                       clocks = <&cpg CPG_MOD 0x9f>,
> > +                                <&cpg CPG_MOD 0xa0>,
> > +                                <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>,
> > +                                <&cpg CPG_MOD 0xa1>;
> > +                       clock-names = "ahb", "axi", "spi", "spix2";
> > +                       assigned-clocks = <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>;
> > +                       assigned-clock-rates = <133333334>;
>
> Do you need these two properties?
> If yes, perhaps they should be moved to the board part?
Yes, I need the above two properties without it flash write operation
fails. Ok I will move them to board DTS.

Cheers,
Prabhakar

Re: [PATCH 2/4] arm64: dts: renesas: r9a09g057: Add XSPI node

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Jul 1, 2025 at 1:08 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, 24 Jun 2025 at 19:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add XSPI node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -280,6 +280,29 @@ sys: system-controller@10430000 {
> >                         resets = <&cpg 0x30>;
> >                 };
> >
> > +               xspi: spi@11030000 {
> > +                       compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
> > +                       reg = <0 0x11030000 0 0x10000>,
> > +                             <0 0x20000000 0 0x10000000>;
> > +                       reg-names = "regs", "dirmap";
> > +                       interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> > +                       interrupt-names = "pulse", "err_pulse";
> > +                       clocks = <&cpg CPG_MOD 0x9f>,
> > +                                <&cpg CPG_MOD 0xa0>,
> > +                                <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>,
> > +                                <&cpg CPG_MOD 0xa1>;
> > +                       clock-names = "ahb", "axi", "spi", "spix2";
> > +                       assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
> > +                       assigned-clock-rates = <133333334>;
>
> Same question as [PATCH 1/4].
>
Sure, I'll move this to the board DTS, and also add the comment below
for clarity.

    /*
     * MT25QU512ABB8E12 flash chip is capable of running at 166MHz
     * clock frequency. Set the maximum clock frequency to 133MHz
     * supported by the RZ/V2H SoC.
     */

Cheers,
Prabhakar