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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id bl19-20020a05620a1a9300b006fa9d101775sm4240295qkb.33.2023.01.09.04.15.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 04:15:52 -0800 (PST) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-482363a1232so110190757b3.3; Mon, 09 Jan 2023 04:15:52 -0800 (PST) X-Received: by 2002:a05:690c:c02:b0:48d:1334:6e38 with SMTP id cl2-20020a05690c0c0200b0048d13346e38mr4982292ywb.316.1673266551917; Mon, 09 Jan 2023 04:15:51 -0800 (PST) MIME-Version: 1.0 References: <20230106185526.260163-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20230106185526.260163-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 9 Jan 2023 13:15:39 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: "Lad, Prabhakar" Cc: Conor Dooley , Arnd Bergmann , Conor Dooley , Heiko Stuebner , Guo Ren , Andrew Jones , Rob Herring , Krzysztof Kozlowski , Lad Prabhakar , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Rob Herring Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Prabhakar, On Sat, Jan 7, 2023 at 9:47 PM Lad, Prabhakar wrote: > On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley wrote: > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote: > > > From: Lad Prabhakar > > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC. > > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch > > > describes the L2 cache block. > > > > > > Signed-off-by: Lad Prabhakar > > > Reviewed-by: Rob Herring > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml > > > @@ -0,0 +1,81 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +# Copyright (C) 2022 Renesas Electronics Corp. > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Andestech AX45MP L2 Cache Controller > > > + > > > +maintainers: > > > + - Lad Prabhakar > > > + > > > +description: > > > + A level-2 cache (L2C) is used to improve the system performance by providing > > > + a large amount of cache line entries and reasonable access delays. The L2C > > > + is shared between cores, and a non-inclusive non-exclusive policy is used. > > > + > > > +select: > > > + properties: > > > + compatible: > > > + contains: > > > + enum: > > > + - andestech,ax45mp-cache > > > + > > > + required: > > > + - compatible > > > + > > > +properties: > > > + compatible: > > > + items: > > > + - const: andestech,ax45mp-cache > > > + - const: cache > > > > You might find value in a specific compatible for your SoC & enforce > > constraints for it. Or you might not & I don't care either way :) > > > Good point actually. Geert what do you think? That might be prudent, to cater for the way the standard AX45MP cache block is integrated into the RZ/Five (or any other) SoC. Still, in the absence of an SoC-specific compatible value, you can handle integration issues using soc_device_match(). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds