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[209.85.128.169]) by smtp.gmail.com with ESMTPSA id bp33-20020a05620a45a100b006e99290e83fsm13454936qkb.107.2023.01.03.00.29.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Jan 2023 00:29:31 -0800 (PST) Received: by mail-yw1-f169.google.com with SMTP id 00721157ae682-482363a1232so272500187b3.3; Tue, 03 Jan 2023 00:29:31 -0800 (PST) X-Received: by 2002:a81:4fcf:0:b0:488:724d:4413 with SMTP id d198-20020a814fcf000000b00488724d4413mr1732163ywb.502.1672734571012; Tue, 03 Jan 2023 00:29:31 -0800 (PST) MIME-Version: 1.0 References: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> <20221221210917.458537-2-fabrizio.castro.jz@renesas.com> In-Reply-To: <20221221210917.458537-2-fabrizio.castro.jz@renesas.com> From: Geert Uytterhoeven Date: Tue, 3 Jan 2023 09:29:19 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 1/4] dt-bindings: mfd: Add RZ/V2M PWC To: fabrizio.castro.jz@renesas.com Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Fabrizio, On Wed, Dec 21, 2022 at 10:09 PM Fabrizio Castro wrote: > The Renesas RZ/V2M External Power Sequence Controller (PWC) > IP is a multi-function device, and it's capable of: > * external power supply on/off sequence generation > * on/off signal generation for the LPDDR4 core power supply (LPVDD) > * key input signals processing > * general-purpose output pins > > Add the corresponding dt-bindings. > > Signed-off-by: Fabrizio Castro > --- > > v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child nodes. Thanks for the update! > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2M External Power Sequence Controller (PWC) > + > +description: |+ > + The PWC IP found in the RZ/V2M family of chips comes with the below > + capabilities > + - external power supply on/off sequence generation > + - on/off signal generation for the LPDDR4 core power supply (LPVDD) > + - key input signals processing > + - general-purpose output pins > + > +maintainers: > + - Fabrizio Castro > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a09g011-pwc # RZ/V2M > + - renesas,r9a09g055-pwc # RZ/V2MA > + - const: renesas,rzv2m-pwc > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + renesas,rzv2m-pwc-power: > + description: The PWC is used to control the system power supplies. > + type: boolean I'm wondering if there is some other way to represent this, e.g. using DT topology? Some regulator relation? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds