[RFC 0/8] Add RZ/G2L POEG support

[RFC 0/8] Add RZ/G2L POEG support

[Biju Das]

The output pins of the general PWM timer (GPT) can be disabled by using
the port output enabling function for the GPT (POEG). Specifically,
either of the following ways can be used.
  * Input level detection of the GTETRGA to GTETRGD pins.
  * Output-disable request from the GPT.
  * Register settings.

Added RZ/G2L POEG support under driver/soc/renesas, as currently I am not sure about
the framework to be used for POEG.

This patch series add support for controlling output disable function using sysfs.

For output disable operation, POEG group needs to be linked with
GPT. So introduced renesas,poeg-group property in pwm for linking both GPT and
POEG devices.

Please share your valuable comments.

patch#3 and #4 depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.das.jz@bp.renesas.com/T/#t

Biju Das (8):
  dt-bindings: soc: renesas: Add RZ/G2L POEG binding
  drivers: soc: renesas: Add POEG driver support
  dt-bindings: pwm: rzg2l-gpt: Document renesas,poeg-group property
  pwm: rzg2l-gpt: Add support for linking with POEG
  arm64: dts: renesas: r9a07g044: Add POEG nodes
  arm64: dts: renesas: r9a07g054: Add POEG nodes
  arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier
    board
  arm64: dts: renesas: rzg2l-smarc: Link GPT4 with POEGGD on carrier
    board

 .../bindings/pwm/renesas,rzg2l-gpt.yaml       |   8 +
 .../soc/renesas/renesas,rzg2l-poeg.yaml       |  65 ++++++++
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |  44 ++++++
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |  44 ++++++
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi  |  17 ++
 drivers/pwm/pwm-rzg2l-gpt.c                   |  59 +++++++
 drivers/soc/renesas/Kconfig                   |   2 +
 drivers/soc/renesas/Makefile                  |   2 +
 drivers/soc/renesas/poeg/Kconfig              |  12 ++
 drivers/soc/renesas/poeg/Makefile             |   2 +
 drivers/soc/renesas/poeg/poeg-rzg2l.c         | 148 ++++++++++++++++++
 11 files changed, 403 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
 create mode 100644 drivers/soc/renesas/poeg/Kconfig
 create mode 100644 drivers/soc/renesas/poeg/Makefile
 create mode 100644 drivers/soc/renesas/poeg/poeg-rzg2l.c

-- 
2.25.1

[RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Biju Das]

Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../soc/renesas/renesas,rzg2l-poeg.yaml       | 65 +++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
new file mode 100644
index 000000000000..5737dbf3fa45
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-poeg.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+  The output pins of the general PWM timer (GPT) can be disabled by using
+  the port output enabling function for the GPT (POEG). Specifically,
+  either of the following ways can be used.
+  * Input level detection of the GTETRGA to GTETRGD pins.
+  * Output-disable request from the GPT.
+  * Register settings.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
+          - renesas,r9a07g054-poeg  # RZ/V2L
+      - const: renesas,rzg2l-poeg
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    poeggd: poeg@10049400 {
+        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
+        reg = <0x10049400 0x4>;
+        interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+        power-domains = <&cpg>;
+        resets = <&cpg R9A07G044_POEG_D_RST>;
+    };
-- 
2.25.1

[RFC 3/8] dt-bindings: pwm: rzg2l-gpt: Document renesas,poeg-group property

[Biju Das]

For output disable operation, POEG group needs to be linked with
GPT. Document renesas,poeg-group property for linking both GPT and
POEG devices.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml        | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index b57c1b256a86..94be441d742c 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -89,6 +89,14 @@ properties:
   resets:
     maxItems: 1
 
+  renesas,poeg-group:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    items:
+      maxItems: 1
+    description:
+      phandle to the POEGGroup instance present in the SoC, one for each
+      available GPT channel.
+
 required:
   - compatible
   - reg
-- 
2.25.1

[RFC 5/8] arm64: dts: renesas: r9a07g044: Add POEG nodes

[Biju Das]

Add POEGG{A,B,C,D} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 28284d537a70..58476519683e 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -360,6 +360,50 @@ gpt7: pwm@10048700 {
 			status = "disabled";
 		};
 
+		poegga: poeg@10048800 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048800 0 0x04>;
+			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_A_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G044_POEG_A_RST>;
+			status = "disabled";
+		};
+
+		poeggb: poeg@10048c00 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048c00 0 0x04>;
+			interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_B_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G044_POEG_B_RST>;
+			status = "disabled";
+		};
+
+		poeggc: poeg@10049000 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049000 0 0x04>;
+			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_C_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G044_POEG_C_RST>;
+			status = "disabled";
+		};
+
+		poeggd: poeg@10049400 {
+			compatible = "renesas,r9a07g044-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049400 0 0x04>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G044_POEG_D_RST>;
+			status = "disabled";
+		};
+
 		ssi0: ssi@10049c00 {
 			compatible = "renesas,r9a07g044-ssi",
 				     "renesas,rz-ssi";
-- 
2.25.1

[RFC 6/8] arm64: dts: renesas: r9a07g054: Add POEG nodes

[Biju Das]

Add POEGG{A,B,C,D} nodes to RZ/V2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 755c92d92e8b..659f0eb11d2b 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -360,6 +360,50 @@ gpt7: pwm@10048700 {
 			status = "disabled";
 		};
 
+		poegga: poeg@10048800 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048800 0 0x04>;
+			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_A_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G054_POEG_A_RST>;
+			status = "disabled";
+		};
+
+		poeggb: poeg@10048C00 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10048C00 0 0x04>;
+			interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_B_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G054_POEG_B_RST>;
+			status = "disabled";
+		};
+
+		poeggc: poeg@10049000 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049000 0 0x04>;
+			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_C_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G054_POEG_C_RST>;
+			status = "disabled";
+		};
+
+		poeggd: poeg@10049400 {
+			compatible = "renesas,r9a07g054-poeg",
+				     "renesas,rzg2l-poeg";
+			reg = <0 0x10049400 0 0x04>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_POEG_D_CLKP>;
+			power-domains = <&cpg>;
+			resets =  <&cpg R9A07G054_POEG_D_RST>;
+			status = "disabled";
+		};
+
 		ssi0: ssi@10049c00 {
 			compatible = "renesas,r9a07g054-ssi",
 				     "renesas,rz-ssi";
-- 
2.25.1

[RFC 7/8] arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier board

[Biju Das]

Enable POEGG{A,B,C,D} on RZ/{G2,V2}L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 8fb68e95f1d7..f1fb9cecc49b 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -42,6 +42,22 @@ wm8978: codec@1a {
 	};
 };
 
+&poegga {
+	status = "okay";
+};
+
+&poeggb {
+	status = "okay";
+};
+
+&poeggc {
+	status = "okay";
+};
+
+&poeggd {
+	status = "okay";
+};
+
 /*
  * To enable SCIF2 (SER0) on PMOD1 (CN7)
  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
-- 
2.25.1

[RFC 8/8] arm64: dts: renesas: rzg2l-smarc: Link GPT4 with POEGGD on carrier board

[Biju Das]

This patch links GPT4 with POEGGD on RZ/G2L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index f1fb9cecc49b..d7cc3897ee61 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -25,6 +25,7 @@ &cpu_dai {
 &gpt4 {
 	pinctrl-0 = <&gpt4_pins>;
 	pinctrl-names = "default";
+	renesas,poeg-group = <&poeggd>;
 	status = "okay";
 };
 
-- 
2.25.1

Re: [RFC 0/8] Add RZ/G2L POEG support

[Uwe Kleine-König]

[-- Attachment #1: Type: text/plain, Size: 1287 bytes --]

On Tue, May 10, 2022 at 04:11:04PM +0100, Biju Das wrote:
> The output pins of the general PWM timer (GPT) can be disabled by using
> the port output enabling function for the GPT (POEG). Specifically,
> either of the following ways can be used.
>   * Input level detection of the GTETRGA to GTETRGD pins.
>   * Output-disable request from the GPT.
>   * Register settings.
> 
> Added RZ/G2L POEG support under driver/soc/renesas, as currently I am not sure about
> the framework to be used for POEG.
> 
> This patch series add support for controlling output disable function using sysfs.
> 
> For output disable operation, POEG group needs to be linked with
> GPT. So introduced renesas,poeg-group property in pwm for linking both GPT and
> POEG devices.
> 
> Please share your valuable comments.
> 
> patch#3 and #4 depend upon [1]
> [1] https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.das.jz@bp.renesas.com/T/#t

I suggest to use the --base switch to git-format-patch for the next
submission round. This way the built robots can parse this information,
too.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

RE: [RFC 0/8] Add RZ/G2L POEG support

[Biju Das]

Hi Uwe,

Thanks for the feedback.

> Subject: Re: [RFC 0/8] Add RZ/G2L POEG support
> 
> On Tue, May 10, 2022 at 04:11:04PM +0100, Biju Das wrote:
> > The output pins of the general PWM timer (GPT) can be disabled by
> > using the port output enabling function for the GPT (POEG).
> > Specifically, either of the following ways can be used.
> >   * Input level detection of the GTETRGA to GTETRGD pins.
> >   * Output-disable request from the GPT.
> >   * Register settings.
> >
> > Added RZ/G2L POEG support under driver/soc/renesas, as currently I am
> > not sure about the framework to be used for POEG.
> >
> > This patch series add support for controlling output disable function
> using sysfs.
> >
> > For output disable operation, POEG group needs to be linked with GPT.
> > So introduced renesas,poeg-group property in pwm for linking both GPT
> > and POEG devices.
> >
> > Please share your valuable comments.
> >
> > patch#3 and #4 depend upon [1]
> > [1]
> > https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.d
> > as.jz@bp.renesas.com/T/#t
> 
> I suggest to use the --base switch to git-format-patch for the next
> submission round. This way the built robots can parse this information,
> too.

Agreed. Will take care this in next submission.

Cheers,
Biju

Re: [RFC 3/8] dt-bindings: pwm: rzg2l-gpt: Document renesas,poeg-group property

[Rob Herring]

On Tue, 10 May 2022 16:11:07 +0100, Biju Das wrote:
> For output disable operation, POEG group needs to be linked with
> GPT. Document renesas,poeg-group property for linking both GPT and
> POEG devices.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml        | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Rob Herring]

On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../soc/renesas/renesas,rzg2l-poeg.yaml       | 65 +++++++++++++++++++
>  1 file changed, 65 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> new file mode 100644
> index 000000000000..5737dbf3fa45
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-poeg.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description:

'|' needed.

> +  The output pins of the general PWM timer (GPT) can be disabled by using
> +  the port output enabling function for the GPT (POEG). Specifically,
> +  either of the following ways can be used.
> +  * Input level detection of the GTETRGA to GTETRGD pins.
> +  * Output-disable request from the GPT.
> +  * Register settings.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
> +          - renesas,r9a07g054-poeg  # RZ/V2L
> +      - const: renesas,rzg2l-poeg
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - power-domains
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    poeggd: poeg@10049400 {
> +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> +        reg = <0x10049400 0x4>;

This looks like it is part of some larger block?

> +        interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A07G044_POEG_D_RST>;
> +    };
> -- 
> 2.25.1
> 
> 

RE: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Biju Das]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> 
> On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> (POEG).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../soc/renesas/renesas,rzg2l-poeg.yaml       | 65 +++++++++++++++++++
> >  1 file changed, 65 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > l
> > b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > l
> > new file mode 100644
> > index 000000000000..5737dbf3fa45
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg
> > +++ .yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
"
> > +
> > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description:
> 
> '|' needed.

OK.

> 
> > +  The output pins of the general PWM timer (GPT) can be disabled by
> > + using  the port output enabling function for the GPT (POEG).
> > + Specifically,  either of the following ways can be used.
> > +  * Input level detection of the GTETRGA to GTETRGD pins.
> > +  * Output-disable request from the GPT.
> > +  * Register settings.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
> > +          - renesas,r9a07g054-poeg  # RZ/V2L
> > +      - const: renesas,rzg2l-poeg
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - power-domains
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    poeggd: poeg@10049400 {
> > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > +        reg = <0x10049400 0x4>;
> 
> This looks like it is part of some larger block?

There are 2 IP blocks GPT(PWM) and POEG with its own resources like (register map, clk, reset and interrupts)

Larger block is GPT, which has lot of functionalities. The output from GPT block can be disabled
by this IP either by external trigger, request from GPT(Deadtime error, both output low/high)
or explicit software control). This IP has only a single register. Currently I am not sure which framework
to be used for this IP?? Or should it be merged with larger block GPT by combining the resources?

Cheers,
Biju


> 
> > +        interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
> > +        power-domains = <&cpg>;
> > +        resets = <&cpg R9A07G044_POEG_D_RST>;
> > +    };
> > --
> > 2.25.1
> >
> >

Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Rob Herring]

On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> Hi Rob,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> > 
> > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> > (POEG).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  .../soc/renesas/renesas,rzg2l-poeg.yaml       | 65 +++++++++++++++++++
> > >  1 file changed, 65 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > > l
> > > b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yam
> > > l
> > > new file mode 100644
> > > index 000000000000..5737dbf3fa45
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg
> > > +++ .yaml
> > > @@ -0,0 +1,65 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> "
> > > +
> > > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > > +
> > > +maintainers:
> > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +description:
> > 
> > '|' needed.
> 
> OK.
> 
> > 
> > > +  The output pins of the general PWM timer (GPT) can be disabled by
> > > + using  the port output enabling function for the GPT (POEG).
> > > + Specifically,  either of the following ways can be used.
> > > +  * Input level detection of the GTETRGA to GTETRGD pins.
> > > +  * Output-disable request from the GPT.
> > > +  * Register settings.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    items:
> > > +      - enum:
> > > +          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
> > > +          - renesas,r9a07g054-poeg  # RZ/V2L
> > > +      - const: renesas,rzg2l-poeg
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  interrupts:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 1
> > > +
> > > +  power-domains:
> > > +    maxItems: 1
> > > +
> > > +  resets:
> > > +    maxItems: 1
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - interrupts
> > > +  - clocks
> > > +  - power-domains
> > > +  - resets
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +    poeggd: poeg@10049400 {
> > > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > > +        reg = <0x10049400 0x4>;
> > 
> > This looks like it is part of some larger block?
> 
> There are 2 IP blocks GPT(PWM) and POEG with its own resources like (register map, clk, reset and interrupts)
> 
> Larger block is GPT, which has lot of functionalities. The output from GPT block can be disabled
> by this IP either by external trigger, request from GPT(Deadtime error, both output low/high)
> or explicit software control). This IP has only a single register. Currently I am not sure which framework
> to be used for this IP?? Or should it be merged with larger block GPT by combining the resources?

Usually, IP blocks would have some minimum address alignment (typ 4K or 
64K to be page aligned), but if there's no other IP in this address 
range as-is is fine. The question is what's before or after the above 
address?

Rob

RE: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Biju Das]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> 
> On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> > Hi Rob,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> > > binding
> > >
> > > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> > > (POEG).
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > >  .../soc/renesas/renesas,rzg2l-poeg.yaml       | 65
> +++++++++++++++++++
> > > >  1 file changed, 65 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.y
> > > > aml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg
> > > > .yam
> > > > l
> > > > b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg
> > > > .yam
> > > > l
> > > > new file mode 100644
> > > > index 000000000000..5737dbf3fa45
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-
> > > > +++ poeg
> > > > +++ .yaml
> > > > @@ -0,0 +1,65 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > "
> > > > +
> > > > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > > > +
> > > > +maintainers:
> > > > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +description:
> > >
> > > '|' needed.
> >
> > OK.
> >
> > >
> > > > +  The output pins of the general PWM timer (GPT) can be disabled
> > > > + by using  the port output enabling function for the GPT (POEG).
> > > > + Specifically,  either of the following ways can be used.
> > > > +  * Input level detection of the GTETRGA to GTETRGD pins.
> > > > +  * Output-disable request from the GPT.
> > > > +  * Register settings.
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    items:
> > > > +      - enum:
> > > > +          - renesas,r9a07g044-poeg  # RZ/G2{L,LC}
> > > > +          - renesas,r9a07g054-poeg  # RZ/V2L
> > > > +      - const: renesas,rzg2l-poeg
> > > > +
> > > > +  reg:
> > > > +    maxItems: 1
> > > > +
> > > > +  interrupts:
> > > > +    maxItems: 1
> > > > +
> > > > +  clocks:
> > > > +    maxItems: 1
> > > > +
> > > > +  power-domains:
> > > > +    maxItems: 1
> > > > +
> > > > +  resets:
> > > > +    maxItems: 1
> > > > +
> > > > +required:
> > > > +  - compatible
> > > > +  - reg
> > > > +  - interrupts
> > > > +  - clocks
> > > > +  - power-domains
> > > > +  - resets
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > +  - |
> > > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > +    poeggd: poeg@10049400 {
> > > > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > > > +        reg = <0x10049400 0x4>;
> > >
> > > This looks like it is part of some larger block?
> >
> > There are 2 IP blocks GPT(PWM) and POEG with its own resources like
> > (register map, clk, reset and interrupts)
> >
> > Larger block is GPT, which has lot of functionalities. The output from
> > GPT block can be disabled by this IP either by external trigger,
> > request from GPT(Deadtime error, both output low/high) or explicit
> > software control). This IP has only a single register. Currently I am not
> sure which framework to be used for this IP?? Or should it be merged with
> larger block GPT by combining the resources?
> 
> Usually, IP blocks would have some minimum address alignment (typ 4K or 64K
> to be page aligned), but if there's no other IP in this address range as-is
> is fine. The question is what's before or after the above address?

As per the HW manual, before GPT IP block and after POE3 block(Port Output Enable 3 (POE3) for MTU).

Before 
H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT

After
H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3

Please find the address map for the IP blocks near to it.


H'0_1004_A000 H'0_1004_A3FF 1 Kbyte SSIF ch1
H'0_1004_9C00 H'0_1004_9FFF 1 Kbyte SSIF ch0
H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
H'0_1004_9400 H'0_1004_97FF 1 Kbyte POEGD
H'0_1004_9000 H'0_1004_93FF 1 Kbyte POEGC
H'0_1004_8C00 H'0_1004_8FFF 1 Kbyte POEGB
H'0_1004_8800 H'0_1004_8BFF 1 Kbyte POEGA
H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
H'0_1004_7000 H'0_1004_7FFF 4 Kbytes SRC (Reg)
H'0_1004_0000 H'0_1004_6FFF 28 Kbytes SRC (Memory)

Cheers,
Biju

Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Geert Uytterhoeven]

Hi Biju,

On Wed, May 18, 2022 at 8:34 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> > On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> > > > binding
> > > >
> > > > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > > > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> > > > (POEG).
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> > > > > +examples:
> > > > > +  - |
> > > > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > +
> > > > > +    poeggd: poeg@10049400 {
> > > > > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
> > > > > +        reg = <0x10049400 0x4>;
> > > >
> > > > This looks like it is part of some larger block?
> > >
> > > There are 2 IP blocks GPT(PWM) and POEG with its own resources like
> > > (register map, clk, reset and interrupts)
> > >
> > > Larger block is GPT, which has lot of functionalities. The output from
> > > GPT block can be disabled by this IP either by external trigger,
> > > request from GPT(Deadtime error, both output low/high) or explicit
> > > software control). This IP has only a single register. Currently I am not
> > sure which framework to be used for this IP?? Or should it be merged with

Yeah, POEG is a weird beast.
Some of it fits under pin control, but not all of it.
From a quick glance, most of its configuration is intended to be
static, i.e. could be done from DT, like pin control?
I have no idea how to use the POEG interrupts, though.

> > larger block GPT by combining the resources?
> >
> > Usually, IP blocks would have some minimum address alignment (typ 4K or 64K
> > to be page aligned), but if there's no other IP in this address range as-is
> > is fine. The question is what's before or after the above address?
>
> As per the HW manual, before GPT IP block and after POE3 block(Port Output Enable 3 (POE3) for MTU).
>
> Before
> H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
>
> After
> H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
>
> Please find the address map for the IP blocks near to it.
>
> H'0_1004_A000 H'0_1004_A3FF 1 Kbyte SSIF ch1
> H'0_1004_9C00 H'0_1004_9FFF 1 Kbyte SSIF ch0
> H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> H'0_1004_9400 H'0_1004_97FF 1 Kbyte POEGD
> H'0_1004_9000 H'0_1004_93FF 1 Kbyte POEGC
> H'0_1004_8C00 H'0_1004_8FFF 1 Kbyte POEGB
> H'0_1004_8800 H'0_1004_8BFF 1 Kbyte POEGA
> H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT

This is actually 8 x 256 bytes, for 8 GPT instances.

> H'0_1004_7000 H'0_1004_7FFF 4 Kbytes SRC (Reg)
> H'0_1004_0000 H'0_1004_6FFF 28 Kbytes SRC (Memory)

So you can combine GPT and POEG[A-D] into a single block.
However, doing so will make life harder when reusing the driver on
an SoC with a different layout, or a different number of POEG blocks
and GPT channels.

BTW, POE3 is a similar (in spirit) block on top of the MTU
(Multi-Function Timer Pulse Unit 3, which seems to be an
 enhanced version of the already-supported MTU2 on RZ/A1?).
But the POE3 block is not located next to the MTU block, so you cannot
combine them without overlap.

Note that the minimum page size on Cortex-A seems to be 4 kiB, and
several blocks are spaced apart less, so even with a different OS
than Linux you cannot implement page-based access control.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> 
> Hi Biju,
> 
> On Wed, May 18, 2022 at 8:34 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> > > binding On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> > > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L
> > > > > POEG binding
> > > > >
> > > > > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > > > > Add device tree bindings for the RZ/G2L Port Output Enable for
> > > > > > GPT
> > > > > (POEG).
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > > > > > +examples:
> > > > > > +  - |
> > > > > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > +
> > > > > > +    poeggd: poeg@10049400 {
> > > > > > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-
> poeg";
> > > > > > +        reg = <0x10049400 0x4>;
> > > > >
> > > > > This looks like it is part of some larger block?
> > > >
> > > > There are 2 IP blocks GPT(PWM) and POEG with its own resources
> > > > like (register map, clk, reset and interrupts)
> > > >
> > > > Larger block is GPT, which has lot of functionalities. The output
> > > > from GPT block can be disabled by this IP either by external
> > > > trigger, request from GPT(Deadtime error, both output low/high) or
> > > > explicit software control). This IP has only a single register.
> > > > Currently I am not
> > > sure which framework to be used for this IP?? Or should it be merged
> > > with
> 
> Yeah, POEG is a weird beast.
> Some of it fits under pin control, but not all of it.
> From a quick glance, most of its configuration is intended to be static,
> i.e. could be done from DT, like pin control?
> I have no idea how to use the POEG interrupts, though.

If there is a GPT request(Dead time error or Both output low/high condition) output is disabled automatically and we get an 
Interrupt. May be to clear it , we need to implement interrupt. Otherwise output will be always disabled,
even if the outputs are out of phase after the fault condition.

I have done a quick test with interrupts previously for output disable using GPT request:- 
	Use both A and B in phase, output is disabled automatically and you get an interrupt in POEG block.
      If you inverse B, it is out of phase and fault condition is no more, but still output is disabled.
      In this condition, If we want to enable outputs, we need to clear interrupt status bits.
            
> 
> > > larger block GPT by combining the resources?
> > >
> > > Usually, IP blocks would have some minimum address alignment (typ 4K
> > > or 64K to be page aligned), but if there's no other IP in this
> > > address range as-is is fine. The question is what's before or after
> the above address?
> >
> > As per the HW manual, before GPT IP block and after POE3 block(Port
> Output Enable 3 (POE3) for MTU).
> >
> > Before
> > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> >
> > After
> > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> >
> > Please find the address map for the IP blocks near to it.
> >
> > H'0_1004_A000 H'0_1004_A3FF 1 Kbyte SSIF ch1
> > H'0_1004_9C00 H'0_1004_9FFF 1 Kbyte SSIF ch0
> > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> > H'0_1004_9400 H'0_1004_97FF 1 Kbyte POEGD
> > H'0_1004_9000 H'0_1004_93FF 1 Kbyte POEGC
> > H'0_1004_8C00 H'0_1004_8FFF 1 Kbyte POEGB
> > H'0_1004_8800 H'0_1004_8BFF 1 Kbyte POEGA
> > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> 
> This is actually 8 x 256 bytes, for 8 GPT instances.

Yes correct.

> 
> > H'0_1004_7000 H'0_1004_7FFF 4 Kbytes SRC (Reg)
> > H'0_1004_0000 H'0_1004_6FFF 28 Kbytes SRC (Memory)
> 
> So you can combine GPT and POEG[A-D] into a single block.
> However, doing so will make life harder when reusing the driver on an SoC
> with a different layout, or a different number of POEG blocks and GPT
> channels.

I agree. Modelling as a different driver gives lots of flexibility.

Cheers,
Biju

> 
> BTW, POE3 is a similar (in spirit) block on top of the MTU (Multi-Function
> Timer Pulse Unit 3, which seems to be an  enhanced version of the already-
> supported MTU2 on RZ/A1?).
> But the POE3 block is not located next to the MTU block, so you cannot
> combine them without overlap.
> 
> Note that the minimum page size on Cortex-A seems to be 4 kiB, and several
> blocks are spaced apart less, so even with a different OS than Linux you
> cannot implement page-based access control.
> 

Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Rob Herring]

On Thu, May 19, 2022 at 09:30:19AM +0000, Biju Das wrote:
> Hi Geert,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding
> > 
> > Hi Biju,
> > 
> > On Wed, May 18, 2022 at 8:34 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> > > > binding On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das wrote:
> > > > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L
> > > > > > POEG binding
> > > > > >
> > > > > > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > > > > > Add device tree bindings for the RZ/G2L Port Output Enable for
> > > > > > > GPT
> > > > > > (POEG).
> > > > > > >
> > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > 
> > > > > > > +examples:
> > > > > > > +  - |
> > > > > > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > > +
> > > > > > > +    poeggd: poeg@10049400 {
> > > > > > > +        compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-
> > poeg";
> > > > > > > +        reg = <0x10049400 0x4>;
> > > > > >
> > > > > > This looks like it is part of some larger block?
> > > > >
> > > > > There are 2 IP blocks GPT(PWM) and POEG with its own resources
> > > > > like (register map, clk, reset and interrupts)
> > > > >
> > > > > Larger block is GPT, which has lot of functionalities. The output
> > > > > from GPT block can be disabled by this IP either by external
> > > > > trigger, request from GPT(Deadtime error, both output low/high) or
> > > > > explicit software control). This IP has only a single register.
> > > > > Currently I am not
> > > > sure which framework to be used for this IP?? Or should it be merged
> > > > with
> > 
> > Yeah, POEG is a weird beast.
> > Some of it fits under pin control, but not all of it.
> > From a quick glance, most of its configuration is intended to be static,
> > i.e. could be done from DT, like pin control?
> > I have no idea how to use the POEG interrupts, though.
> 
> If there is a GPT request(Dead time error or Both output low/high condition) output is disabled automatically and we get an 
> Interrupt. May be to clear it , we need to implement interrupt. Otherwise output will be always disabled,
> even if the outputs are out of phase after the fault condition.
> 
> I have done a quick test with interrupts previously for output disable using GPT request:- 
> 	Use both A and B in phase, output is disabled automatically and you get an interrupt in POEG block.
>       If you inverse B, it is out of phase and fault condition is no more, but still output is disabled.
>       In this condition, If we want to enable outputs, we need to clear interrupt status bits.
>             
> > 
> > > > larger block GPT by combining the resources?
> > > >
> > > > Usually, IP blocks would have some minimum address alignment (typ 4K
> > > > or 64K to be page aligned), but if there's no other IP in this
> > > > address range as-is is fine. The question is what's before or after
> > the above address?
> > >
> > > As per the HW manual, before GPT IP block and after POE3 block(Port
> > Output Enable 3 (POE3) for MTU).
> > >
> > > Before
> > > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> > >
> > > After
> > > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> > >
> > > Please find the address map for the IP blocks near to it.
> > >
> > > H'0_1004_A000 H'0_1004_A3FF 1 Kbyte SSIF ch1
> > > H'0_1004_9C00 H'0_1004_9FFF 1 Kbyte SSIF ch0
> > > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> > > H'0_1004_9400 H'0_1004_97FF 1 Kbyte POEGD
> > > H'0_1004_9000 H'0_1004_93FF 1 Kbyte POEGC
> > > H'0_1004_8C00 H'0_1004_8FFF 1 Kbyte POEGB
> > > H'0_1004_8800 H'0_1004_8BFF 1 Kbyte POEGA
> > > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> > 
> > This is actually 8 x 256 bytes, for 8 GPT instances.
> 
> Yes correct.
> 
> > 
> > > H'0_1004_7000 H'0_1004_7FFF 4 Kbytes SRC (Reg)
> > > H'0_1004_0000 H'0_1004_6FFF 28 Kbytes SRC (Memory)
> > 
> > So you can combine GPT and POEG[A-D] into a single block.
> > However, doing so will make life harder when reusing the driver on an SoC
> > with a different layout, or a different number of POEG blocks and GPT
> > channels.
> 
> I agree. Modelling as a different driver gives lots of flexibility.

The question is different h/w blocks or 1, not driver(s). It's 
convenient when the answer is the same (i.e. h/w node:driver is 1:1), 
but h/w is sometimes messy.

In any case, that looks like different blocks to me.

Rob

RE: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG binding

[Biju Das]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> binding
> 
> On Thu, May 19, 2022 at 09:30:19AM +0000, Biju Das wrote:
> > Hi Geert,
> >
> > Thanks for the feedback.
> >
> > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L POEG
> > > binding
> > >
> > > Hi Biju,
> > >
> > > On Wed, May 18, 2022 at 8:34 PM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L
> > > > > POEG binding On Wed, May 18, 2022 at 05:58:00AM +0000, Biju Das
> wrote:
> > > > > > > Subject: Re: [RFC 1/8] dt-bindings: soc: renesas: Add RZ/G2L
> > > > > > > POEG binding
> > > > > > >
> > > > > > > On Tue, May 10, 2022 at 04:11:05PM +0100, Biju Das wrote:
> > > > > > > > Add device tree bindings for the RZ/G2L Port Output Enable
> > > > > > > > for GPT
> > > > > > > (POEG).
> > > > > > > >
> > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > > > > > > +examples:
> > > > > > > > +  - |
> > > > > > > > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > > > > > > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > > > +
> > > > > > > > +    poeggd: poeg@10049400 {
> > > > > > > > +        compatible = "renesas,r9a07g044-poeg",
> > > > > > > > + "renesas,rzg2l-
> > > poeg";
> > > > > > > > +        reg = <0x10049400 0x4>;
> > > > > > >
> > > > > > > This looks like it is part of some larger block?
> > > > > >
> > > > > > There are 2 IP blocks GPT(PWM) and POEG with its own resources
> > > > > > like (register map, clk, reset and interrupts)
> > > > > >
> > > > > > Larger block is GPT, which has lot of functionalities. The
> > > > > > output from GPT block can be disabled by this IP either by
> > > > > > external trigger, request from GPT(Deadtime error, both output
> > > > > > low/high) or explicit software control). This IP has only a
> single register.
> > > > > > Currently I am not
> > > > > sure which framework to be used for this IP?? Or should it be
> > > > > merged with
> > >
> > > Yeah, POEG is a weird beast.
> > > Some of it fits under pin control, but not all of it.
> > > From a quick glance, most of its configuration is intended to be
> > > static, i.e. could be done from DT, like pin control?
> > > I have no idea how to use the POEG interrupts, though.
> >
> > If there is a GPT request(Dead time error or Both output low/high
> > condition) output is disabled automatically and we get an Interrupt.
> > May be to clear it , we need to implement interrupt. Otherwise output
> will be always disabled, even if the outputs are out of phase after the
> fault condition.
> >
> > I have done a quick test with interrupts previously for output disable
> using GPT request:-
> > 	Use both A and B in phase, output is disabled automatically and
> you get an interrupt in POEG block.
> >       If you inverse B, it is out of phase and fault condition is no
> more, but still output is disabled.
> >       In this condition, If we want to enable outputs, we need to
> clear interrupt status bits.
> >
> > >
> > > > > larger block GPT by combining the resources?
> > > > >
> > > > > Usually, IP blocks would have some minimum address alignment
> > > > > (typ 4K or 64K to be page aligned), but if there's no other IP
> > > > > in this address range as-is is fine. The question is what's
> > > > > before or after
> > > the above address?
> > > >
> > > > As per the HW manual, before GPT IP block and after POE3
> > > > block(Port
> > > Output Enable 3 (POE3) for MTU).
> > > >
> > > > Before
> > > > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> > > >
> > > > After
> > > > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> > > >
> > > > Please find the address map for the IP blocks near to it.
> > > >
> > > > H'0_1004_A000 H'0_1004_A3FF 1 Kbyte SSIF ch1
> > > > H'0_1004_9C00 H'0_1004_9FFF 1 Kbyte SSIF ch0
> > > > H'0_1004_9800 H'0_1004_9BFF 1 Kbyte POE3
> > > > H'0_1004_9400 H'0_1004_97FF 1 Kbyte POEGD
> > > > H'0_1004_9000 H'0_1004_93FF 1 Kbyte POEGC
> > > > H'0_1004_8C00 H'0_1004_8FFF 1 Kbyte POEGB
> > > > H'0_1004_8800 H'0_1004_8BFF 1 Kbyte POEGA
> > > > H'0_1004_8000 H'0_1004_87FF 2 Kbytes GPT
> > >
> > > This is actually 8 x 256 bytes, for 8 GPT instances.
> >
> > Yes correct.
> >
> > >
> > > > H'0_1004_7000 H'0_1004_7FFF 4 Kbytes SRC (Reg)
> > > > H'0_1004_0000 H'0_1004_6FFF 28 Kbytes SRC (Memory)
> > >
> > > So you can combine GPT and POEG[A-D] into a single block.
> > > However, doing so will make life harder when reusing the driver on
> > > an SoC with a different layout, or a different number of POEG blocks
> > > and GPT channels.
> >
> > I agree. Modelling as a different driver gives lots of flexibility.
> 
> The question is different h/w blocks or 1, not driver(s). It's
> convenient when the answer is the same (i.e. h/w node:driver is 1:1),
> but h/w is sometimes messy.
> 
> In any case, that looks like different blocks to me.

OK, As Geert suggested will model this block as pinctrl.

Cheers,
Biju