* [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support [not found] <20210121100619.5653-1-wsa+renesas@sang-engineering.com> @ 2021-01-21 10:06 ` Wolfram Sang 2021-01-23 3:31 ` Jakub Kicinski 2021-01-21 10:06 ` [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support Wolfram Sang ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Wolfram Sang @ 2021-01-21 10:06 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Geert Uytterhoeven, Rob Herring, Sergei Shtylyov, David S. Miller, Jakub Kicinski, Rob Herring, netdev, devicetree, linux-kernel Document the compatible value for the RAVB block in the Renesas R-Car V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need to add the new compatible and add it to the TX delay block. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Please apply via netdev tree. Change since v1: * add entry to TX delay block * added tags Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 244befb6402a..c4c441c493ff 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -40,6 +40,7 @@ properties: - renesas,etheravb-r8a77980 # R-Car V3H - renesas,etheravb-r8a77990 # R-Car E3 - renesas,etheravb-r8a77995 # R-Car D3 + - renesas,etheravb-r8a779a0 # R-Car V3U - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2 reg: true @@ -169,6 +170,7 @@ allOf: - renesas,etheravb-r8a77965 - renesas,etheravb-r8a77970 - renesas,etheravb-r8a77980 + - renesas,etheravb-r8a779a0 then: required: - tx-internal-delay-ps -- 2.29.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support 2021-01-21 10:06 ` [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support Wolfram Sang @ 2021-01-23 3:31 ` Jakub Kicinski 0 siblings, 0 replies; 9+ messages in thread From: Jakub Kicinski @ 2021-01-23 3:31 UTC (permalink / raw) To: Wolfram Sang Cc: linux-renesas-soc, Geert Uytterhoeven, Rob Herring, Sergei Shtylyov, David S. Miller, Rob Herring, netdev, devicetree, linux-kernel On Thu, 21 Jan 2021 11:06:15 +0100 Wolfram Sang wrote: > Document the compatible value for the RAVB block in the Renesas R-Car > V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need > to add the new compatible and add it to the TX delay block. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > > Please apply via netdev tree. Done, thank you! ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support [not found] <20210121100619.5653-1-wsa+renesas@sang-engineering.com> 2021-01-21 10:06 ` [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support Wolfram Sang @ 2021-01-21 10:06 ` Wolfram Sang 2021-01-22 10:20 ` Geert Uytterhoeven 2021-01-21 10:06 ` [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support Wolfram Sang 2021-01-21 10:06 ` [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support Wolfram Sang 3 siblings, 1 reply; 9+ messages in thread From: Wolfram Sang @ 2021-01-21 10:06 UTC (permalink / raw) To: linux-renesas-soc Cc: Tho Vu, Geert Uytterhoeven, Wolfram Sang, Magnus Damm, Rob Herring, devicetree, linux-kernel From: Tho Vu <tho.vu.wh@renesas.com> Define the generic parts of Ethernet-AVB device nodes. Only AVB0 was tested because it was the only port with a PHY on current hardware. Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> [wsa: double checked, rebased, added "internal-delay" properties] Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Change since v1: * added internal-delay properties arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 282 ++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 1d953a892309..4671a5840ae1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -372,6 +372,288 @@ i2c6: i2c@e66e8000 { status = "disabled"; }; + avb0: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 211>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb1: ethernet@e6810000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6810000 0 0x800>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 212>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 212>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb2: ethernet@e6820000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6820000 0 0x1000>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 213>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 213>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb3: ethernet@e6830000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6830000 0 0x1000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 214>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 214>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb4: ethernet@e6840000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6840000 0 0x1000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 215>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 215>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + avb5: ethernet@e6850000 { + compatible = "renesas,etheravb-r8a779a0", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6850000 0 0x1000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 216>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 216>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", "renesas,rcar-gen3-scif", "renesas,scif"; -- 2.29.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support 2021-01-21 10:06 ` [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support Wolfram Sang @ 2021-01-22 10:20 ` Geert Uytterhoeven 0 siblings, 0 replies; 9+ messages in thread From: Geert Uytterhoeven @ 2021-01-22 10:20 UTC (permalink / raw) To: Wolfram Sang Cc: Linux-Renesas, Tho Vu, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List On Thu, Jan 21, 2021 at 11:06 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > From: Tho Vu <tho.vu.wh@renesas.com> > > Define the generic parts of Ethernet-AVB device nodes. Only AVB0 was > tested because it was the only port with a PHY on current hardware. > > Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> > [wsa: double checked, rebased, added "internal-delay" properties] > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > Change since v1: > * added internal-delay properties Will queue in renesas-devel for v5.12. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support [not found] <20210121100619.5653-1-wsa+renesas@sang-engineering.com> 2021-01-21 10:06 ` [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support Wolfram Sang 2021-01-21 10:06 ` [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support Wolfram Sang @ 2021-01-21 10:06 ` Wolfram Sang 2021-01-22 10:23 ` Geert Uytterhoeven 2021-01-21 10:06 ` [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support Wolfram Sang 3 siblings, 1 reply; 9+ messages in thread From: Wolfram Sang @ 2021-01-21 10:06 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, devicetree, linux-kernel Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Change since v1: * removed avb1-5 which couldn't be tested * added alias for avb0 so firmware can add MAC address * added custom tx-internal-delay-ps * dropped '_tx' suffix from 'pins_mii' config * moved entries to Falcon CPU dtsi .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 35 +++++++++++++++++++ .../boot/dts/renesas/r8a779a0-falcon.dts | 1 + 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 6dcd4683b071..f96b03f39787 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +#include <dt-bindings/gpio/gpio.h> #include "r8a779a0.dtsi" / { @@ -33,6 +34,22 @@ memory@700000000 { }; }; +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -98,6 +115,24 @@ &i2c6 { }; &pfc { + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index fb9978ea18f4..5617b81dd7dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -13,6 +13,7 @@ / { compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; aliases { + ethernet0 = &avb0; serial0 = &scif0; }; -- 2.29.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support 2021-01-21 10:06 ` [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support Wolfram Sang @ 2021-01-22 10:23 ` Geert Uytterhoeven 0 siblings, 0 replies; 9+ messages in thread From: Geert Uytterhoeven @ 2021-01-22 10:23 UTC (permalink / raw) To: Wolfram Sang Cc: Linux-Renesas, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List On Thu, Jan 21, 2021 at 11:06 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > Change since v1: > > * removed avb1-5 which couldn't be tested > * added alias for avb0 so firmware can add MAC address > * added custom tx-internal-delay-ps > * dropped '_tx' suffix from 'pins_mii' config > * moved entries to Falcon CPU dtsi Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.12. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support [not found] <20210121100619.5653-1-wsa+renesas@sang-engineering.com> ` (2 preceding siblings ...) 2021-01-21 10:06 ` [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support Wolfram Sang @ 2021-01-21 10:06 ` Wolfram Sang 2021-01-22 10:26 ` Geert Uytterhoeven 3 siblings, 1 reply; 9+ messages in thread From: Wolfram Sang @ 2021-01-21 10:06 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, devicetree, linux-kernel PHYs on the subboard could not be reached via remote access. But this is the latest DTS snipplet with some fixes suggested by Geert as a starting point. Not for upstream yet! Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Change since v1: * new patch * removed rxc-skew-ps property * renamed phy-addresses to 0 ('@0') * dropped '_tx' suffix from 'pins_mii' config * added 'okay' status * moved entries to Falcon CPU dtsi .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index f96b03f39787..0059381443f6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -50,6 +50,81 @@ phy0: ethernet-phy@0 { }; }; +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy1: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&phy2>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy2: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + }; +}; + +&avb3 { + pinctrl-0 = <&avb3_pins>; + pinctrl-names = "default"; + phy-handle = <&phy3>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy3: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + }; +}; + +&avb4 { + pinctrl-0 = <&avb4_pins>; + pinctrl-names = "default"; + phy-handle = <&phy4>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy4: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio8>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>; + }; +}; + +&avb5 { + pinctrl-0 = <&avb5_pins>; + pinctrl-names = "default"; + phy-handle = <&phy5>; + phy-mode = "rgmii-txid"; + status = "okay"; + + phy5: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio9>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -133,6 +208,91 @@ pins_mii { }; + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", "avb1_txcrefclk"; + function = "avb1"; + }; + + pins_mdio { + groups = "avb1_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb1_rgmii"; + drive-strength = <21>; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", "avb2_txcrefclk"; + function = "avb2"; + }; + + pins_mdio { + groups = "avb2_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb2_rgmii"; + drive-strength = <21>; + }; + }; + + avb3_pins: avb3 { + mux { + groups = "avb3_link", "avb3_mdio", "avb3_rgmii", "avb3_txcrefclk"; + function = "avb3"; + }; + + pins_mdio { + groups = "avb3_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb3_rgmii"; + drive-strength = <21>; + }; + }; + + avb4_pins: avb4 { + mux { + groups = "avb4_link", "avb4_mdio", "avb4_rgmii", "avb4_txcrefclk"; + function = "avb4"; + }; + + pins_mdio { + groups = "avb4_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb4_rgmii"; + drive-strength = <21>; + }; + }; + + avb5_pins: avb5 { + mux { + groups = "avb5_link", "avb5_mdio", "avb5_rgmii", "avb5_txcrefclk"; + function = "avb5"; + }; + + pins_mdio { + groups = "avb5_mdio"; + drive-strength = <21>; + }; + + ins_mii { + groups = "avb5_rgmii"; + drive-strength = <21>; + }; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; -- 2.29.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support 2021-01-21 10:06 ` [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support Wolfram Sang @ 2021-01-22 10:26 ` Geert Uytterhoeven 2021-01-22 10:47 ` Wolfram Sang 0 siblings, 1 reply; 9+ messages in thread From: Geert Uytterhoeven @ 2021-01-22 10:26 UTC (permalink / raw) To: Wolfram Sang Cc: Linux-Renesas, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List Hi Wolfram, On Thu, Jan 21, 2021 at 11:06 AM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > PHYs on the subboard could not be reached via remote access. But this is > the latest DTS snipplet with some fixes suggested by Geert as a starting > point. Not for upstream yet! > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > Change since v1: > > * new patch > * removed rxc-skew-ps property > * renamed phy-addresses to 0 ('@0') > * dropped '_tx' suffix from 'pins_mii' config > * added 'okay' status > * moved entries to Falcon CPU dtsi Thanks for the update! > .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 160 ++++++++++++++++++ New file r8a779a0-falcon-ether.dtsi? > + avb5_pins: avb5 { > + mux { > + groups = "avb5_link", "avb5_mdio", "avb5_rgmii", "avb5_txcrefclk"; > + function = "avb5"; > + }; > + > + pins_mdio { > + groups = "avb5_mdio"; > + drive-strength = <21>; > + }; > + > + ins_mii { pins_mii > + groups = "avb5_rgmii"; > + drive-strength = <21>; > + }; > + }; > + Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support 2021-01-22 10:26 ` Geert Uytterhoeven @ 2021-01-22 10:47 ` Wolfram Sang 0 siblings, 0 replies; 9+ messages in thread From: Wolfram Sang @ 2021-01-22 10:47 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Linux-Renesas, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List [-- Attachment #1: Type: text/plain, Size: 231 bytes --] > > .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 160 ++++++++++++++++++ > > New file r8a779a0-falcon-ether.dtsi? Makes sense. > > > + ins_mii { > > pins_mii Now, how did that happen? Thanks! [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-01-23 3:32 UTC | newest]
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[not found] <20210121100619.5653-1-wsa+renesas@sang-engineering.com>
2021-01-21 10:06 ` [PATCH v2 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support Wolfram Sang
2021-01-23 3:31 ` Jakub Kicinski
2021-01-21 10:06 ` [PATCH v2 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support Wolfram Sang
2021-01-22 10:20 ` Geert Uytterhoeven
2021-01-21 10:06 ` [PATCH v2 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB0 support Wolfram Sang
2021-01-22 10:23 ` Geert Uytterhoeven
2021-01-21 10:06 ` [PATCH v2 5/5] WIP! arm64: dts: renesas: falcon: Add Ethernet-AVB1-5 support Wolfram Sang
2021-01-22 10:26 ` Geert Uytterhoeven
2021-01-22 10:47 ` Wolfram Sang
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