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[209.85.128.179]) by smtp.gmail.com with ESMTPSA id d70-20020a814f49000000b005fdc47c460dsm285001ywb.23.2024.01.15.08.48.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Jan 2024 08:48:30 -0800 (PST) Received: by mail-yw1-f179.google.com with SMTP id 00721157ae682-5f0c0ca5ef1so87109787b3.2; Mon, 15 Jan 2024 08:48:30 -0800 (PST) X-Received: by 2002:a05:690c:a98:b0:5e9:f386:dd63 with SMTP id ci24-20020a05690c0a9800b005e9f386dd63mr4282644ywb.39.1705337310443; Mon, 15 Jan 2024 08:48:30 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240115-wages-secluded-b44f4eb13323@spud> In-Reply-To: <20240115-wages-secluded-b44f4eb13323@spud> From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 17:48:18 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] dt-bindings: timer: renesas,tmu: Document input capture interrupt To: Conor Dooley Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Laurent Pinchart , Yoshinori Sato , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Conor, On Mon, Jan 15, 2024 at 5:13=E2=80=AFPM Conor Dooley wro= te: > On Mon, Jan 15, 2024 at 02:45:39PM +0100, Geert Uytterhoeven wrote: > > Some Timer Unit (TMU) instances with 3 channels support a fourth > > interrupt: an input capture interrupt for the third channel. > > > > While at it, document the meaning of the four interrupts, and add > > "interrupt-names" for clarity. > > > > Update the example to match reality. > > > > Inspired by a patch by Yoshinori Sato for SH. > > > > Signed-off-by: Geert Uytterhoeven > > --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml > > +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml > > @@ -46,7 +46,19 @@ properties: > > > > interrupts: > > minItems: 2 > > - maxItems: 3 > > + items: > > + - description: Underflow interrupt 0 > > + - description: Underflow interrupt 1 > > + - description: Underflow interrupt 2 > > + - description: Input capture interrupt 2 > > Seeing "input capture interrupt 2" makes me wonder, are there two (or > more!) other input capture interrupts that are still out there, > undocumented, and looking for a home? SoCs can have multiple TMU instances. Each TMU instance has 2 or 3 timer channels. Each timer channel has an underflow interrupt. Only the third channel may have an optional input capture interrupt (which is not supported yet by the Linux driver). Hence each instance can have 2, 3, or 4 interrupts. See "RZ/G Series, 2nd Generation User's Manual: Hardware"[1], Section 69 ("Timer Unit (TMU)": - Figure 69.2: Block Diagram of TMU, - Section 69: Interrupt Note that the documentation uses a monotonic increasing numbering of the channels, across all instances. [1] https://www.renesas.com/us/en/products/microcontrollers-microprocessors= /rz-mpus/rzg2h-ultra-high-performance-microprocessors-quad-core-arm-cortex-= a57-and-quad-core-arm-cortex-a53-cpus-3d Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds