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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,  Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Magnus Damm <magnus.damm@gmail.com>,
	linux-renesas-soc@vger.kernel.org,  linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org,  devicetree@vger.kernel.org,
	Biju Das <biju.das.jz@bp.renesas.com>,
	 Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks
Date: Tue, 15 Apr 2025 16:58:12 +0200	[thread overview]
Message-ID: <CAMuHMdWZisqxyGL32Y-AD1UgQD9fWKG+a-o71R+KeuSqn=U6gQ@mail.gmail.com> (raw)
In-Reply-To: <20250407165202.197570-7-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Ignore CLK_MON bits when turning on/off module clocks that use an external
> clock source.
>
> Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> to update mon_index.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
>         spin_unlock_irqrestore(&priv->rmw_lock, flags);
>  }
>
> +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> +                                       u16 ext_clk_offset,
> +                                       u8 ext_clk_bit,
> +                                       u8 ext_cond)
> +{
> +       u32 value;
> +
> +       if (!ext_clk_offset)
> +               return false;
> +
> +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);

As ext_clk_offset is actually the offset of the Static Mux Control
Registers (CPG_SSELm), this reads the current state of the mux.
However, can't the state be changed at runtime (despite it being named
a "static mux")?

> +       value >>= ext_clk_bit;
> +
> +       if (value == ext_cond)
> +               return true;
> +
> +       return false;
> +}
> +
>  static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
>  {
>         struct mod_clock *clock = to_mod_clock(hw);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  parent reply	other threads:[~2025-04-15 14:58 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-07 16:51 [PATCH v2 0/9] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH Prabhakar
2025-04-07 16:51 ` [PATCH v2 1/9] clk: renesas: rzv2h-cpg: Add support for static mux clocks Prabhakar
2025-04-15 14:34   ` Geert Uytterhoeven
2025-04-07 16:51 ` [PATCH v2 2/9] clk: renesas: rzv2h-cpg: Add macro for defining static dividers Prabhakar
2025-04-15 14:34   ` Geert Uytterhoeven
2025-04-07 16:51 ` [PATCH v2 3/9] clk: renesas: rzv2h-cpg: Support static dividers without RMW Prabhakar
2025-04-15 14:34   ` Geert Uytterhoeven
2025-04-07 16:51 ` [PATCH v2 4/9] clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable() Prabhakar
2025-04-15 13:12   ` Geert Uytterhoeven
2025-04-07 16:51 ` [PATCH v2 5/9] clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation Prabhakar
2025-04-15 14:35   ` Geert Uytterhoeven
2025-04-07 16:51 ` [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks Prabhakar
2025-04-15 14:36   ` Geert Uytterhoeven
2025-04-15 19:10     ` Lad, Prabhakar
2025-04-15 14:58   ` Geert Uytterhoeven [this message]
2025-04-15 19:12     ` Lad, Prabhakar
2025-04-07 16:52 ` [PATCH v2 7/9] dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks Prabhakar
2025-04-15 14:36   ` Geert Uytterhoeven
2025-04-07 16:52 ` [PATCH v2 8/9] clk: renesas: r9a09g057: Add clock and reset entries for USB2 Prabhakar
2025-04-15 14:36   ` Geert Uytterhoeven
2025-04-07 16:52 ` [PATCH v2 9/9] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1 Prabhakar
2025-04-15 14:36   ` Geert Uytterhoeven
2025-04-15 19:24     ` Lad, Prabhakar
2025-04-16  7:37       ` Geert Uytterhoeven
2025-04-17 13:58         ` Lad, Prabhakar
2025-04-15 14:54   ` Geert Uytterhoeven
2025-04-28 13:22     ` Lad, Prabhakar
2025-04-28 13:36       ` Geert Uytterhoeven
2025-04-28 15:54         ` Lad, Prabhakar

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