* [PATCH v2 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding
2022-11-24 19:16 [PATCH v2 0/5] Add RZ/V2{M, MA} PWM driver support Biju Das
@ 2022-11-24 19:16 ` Biju Das
2022-12-01 16:23 ` Geert Uytterhoeven
2022-11-24 19:16 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g011: Add pwm nodes Biju Das
2022-11-24 19:16 ` [PATCH v2 5/5] arm64: dts: renesas: rzv2m evk: Enable pwm Biju Das
2 siblings, 1 reply; 7+ messages in thread
From: Biju Das @ 2022-11-24 19:16 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Uwe Kleine-König, linux-pwm, devicetree,
Geert Uytterhoeven, Fabrizio Castro, linux-renesas-soc,
Krzysztof Kozlowski
Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v1->v2:
* Added Rb tag from Krzysztof and the keep the Rb tag as the below changes
are trivial
* Updated the description for APB clock
* Added resets required property
* Updated the example with resets property
---
.../bindings/pwm/renesas,rzv2m-pwm.yaml | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
new file mode 100644
index 000000000000..ddeed7550923
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2{M, MA} PWM Timer (PWM)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the
+ following functions
+ * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
+ * The frequency division ratio for internal counter operation is selectable
+ as PWM_CLK divided by 1, 16, 256, or 2048.
+ * The period as well as the duty cycle is adjustable.
+ * The low-level and high-level order of the PWM signals can be inverted.
+ * The duty cycle of the PWM signal is selectable in the range from 0 to 100%.
+ * The minimum resolution is 20.83 ns.
+ * Three interrupt sources: Rising and falling edges of the PWM signal and
+ clearing of the counter
+ * Counter operation and the bus interface are asynchronous and both can
+ operate independently of the magnitude relationship of the respective
+ clock periods.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a09g011-pwm # RZ/V2M
+ - renesas,r9a09g055-pwm # RZ/V2MA
+ - const: renesas,rzv2m-pwm
+
+ reg:
+ maxItems: 1
+
+ '#pwm-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB clock
+ - description: PWM clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: pwm
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a09g011-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pwm8: pwm@a4010400 {
+ compatible = "renesas,r9a09g011-pwm", "renesas,rzv2m-pwm";
+ reg = <0xa4010400 0x80>;
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM8_CLK>;
+ clock-names = "apb", "pwm";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ #pwm-cells = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding
2022-11-24 19:16 ` [PATCH v2 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding Biju Das
@ 2022-12-01 16:23 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2022-12-01 16:23 UTC (permalink / raw)
To: Biju Das
Cc: Thierry Reding, Rob Herring, Krzysztof Kozlowski,
Uwe Kleine-König, linux-pwm, devicetree, Fabrizio Castro,
linux-renesas-soc, Krzysztof Kozlowski
On Thu, Nov 24, 2022 at 8:17 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> v1->v2:
> * Added Rb tag from Krzysztof and the keep the Rb tag as the below changes
> are trivial
> * Updated the description for APB clock
> * Added resets required property
> * Updated the example with resets property
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 4/5] arm64: dts: renesas: r9a09g011: Add pwm nodes
2022-11-24 19:16 [PATCH v2 0/5] Add RZ/V2{M, MA} PWM driver support Biju Das
2022-11-24 19:16 ` [PATCH v2 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding Biju Das
@ 2022-11-24 19:16 ` Biju Das
2022-12-01 16:25 ` Geert Uytterhoeven
2022-11-24 19:16 ` [PATCH v2 5/5] arm64: dts: renesas: rzv2m evk: Enable pwm Biju Das
2 siblings, 1 reply; 7+ messages in thread
From: Biju Das @ 2022-11-24 19:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro
Add device nodes for the pwm timer channels that are not assigned
to the ISP.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Added resets property
---
arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 98 ++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
index 0373ec409d54..dcd3a05e54fe 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi
@@ -135,6 +135,104 @@ sys: system-controller@a3f03000 {
reg = <0 0xa3f03000 0 0x400>;
};
+ pwm8: pwm@a4010400 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010400 0 0x80>;
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM8_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm9: pwm@a4010480 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010480 0 0x80>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM9_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm10: pwm@a4010500 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010500 0 0x80>;
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM10_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm11: pwm@a4010580 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010580 0 0x80>;
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM11_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm12: pwm@a4010600 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010600 0 0x80>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM12_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm13: pwm@a4010680 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010680 0 0x80>;
+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM13_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm14: pwm@a4010700 {
+ compatible = "renesas,r9a09g011-pwm",
+ "renesas,rzv2m-pwm";
+ reg = <0 0xa4010700 0 0x80>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>,
+ <&cpg CPG_MOD R9A09G011_PWM14_CLK>;
+ clock-names = "apb", "pwm";
+ resets = <&cpg R9A09G011_PWM_GPF_PRESETN>;
+ power-domains = <&cpg>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 4/5] arm64: dts: renesas: r9a09g011: Add pwm nodes
2022-11-24 19:16 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g011: Add pwm nodes Biju Das
@ 2022-12-01 16:25 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2022-12-01 16:25 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro
On Thu, Nov 24, 2022 at 8:17 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add device nodes for the pwm timer channels that are not assigned
> to the ISP.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Added resets property
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 5/5] arm64: dts: renesas: rzv2m evk: Enable pwm
2022-11-24 19:16 [PATCH v2 0/5] Add RZ/V2{M, MA} PWM driver support Biju Das
2022-11-24 19:16 ` [PATCH v2 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding Biju Das
2022-11-24 19:16 ` [PATCH v2 4/5] arm64: dts: renesas: r9a09g011: Add pwm nodes Biju Das
@ 2022-11-24 19:16 ` Biju Das
2022-12-01 16:34 ` Geert Uytterhoeven
2 siblings, 1 reply; 7+ messages in thread
From: Biju Das @ 2022-11-24 19:16 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro
Enable pwm{8..14} on RZ/V2M EVK.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change
---
.../boot/dts/renesas/r9a09g011-v2mevk2.dts | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
index 11e1d51c7c0e..73d7481b468e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
@@ -78,6 +78,76 @@ i2c2_pins: i2c2 {
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
};
+
+ pwm8_pins: pwm8 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 8, 1)>; /* PM8 */
+ };
+
+ pwm9_pins: pwm9 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 9, 1)>; /* PM9 */
+ };
+
+ pwm10_pins: pwm10 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 10, 1)>; /* PM10 */
+ };
+
+ pwm11_pins: pwm11 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 11, 1)>; /* PM11 */
+ };
+
+ pwm12_pins: pwm12 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 12, 1)>; /* PM12 */
+ };
+
+ pwm13_pins: pwm13 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 13, 1)>; /* PM13 */
+ };
+
+ pwm14_pins: pwm14 {
+ pinmux = <RZV2M_PORT_PINMUX(1, 14, 1)>; /* PM14 */
+ };
+};
+
+&pwm8 {
+ pinctrl-0 = <&pwm8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm9 {
+ pinctrl-0 = <&pwm9_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm10 {
+ pinctrl-0 = <&pwm10_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm11 {
+ pinctrl-0 = <&pwm11_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm12 {
+ pinctrl-0 = <&pwm12_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm13 {
+ pinctrl-0 = <&pwm13_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm14 {
+ pinctrl-0 = <&pwm14_pins>;
+ pinctrl-names = "default";
+ status = "okay";
};
&uart0 {
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 5/5] arm64: dts: renesas: rzv2m evk: Enable pwm
2022-11-24 19:16 ` [PATCH v2 5/5] arm64: dts: renesas: rzv2m evk: Enable pwm Biju Das
@ 2022-12-01 16:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 7+ messages in thread
From: Geert Uytterhoeven @ 2022-12-01 16:34 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, linux-renesas-soc,
devicetree, Fabrizio Castro
On Thu, Nov 24, 2022 at 8:17 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable pwm{8..14} on RZ/V2M EVK.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 7+ messages in thread