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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6e2bbea6e6esm5506567b3.50.2024.10.04.00.13.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Oct 2024 00:13:54 -0700 (PDT) Received: by mail-yw1-f173.google.com with SMTP id 00721157ae682-6dbb24ee34dso15578737b3.2; Fri, 04 Oct 2024 00:13:54 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWlZgddq9NoyqfwAVbQM07r2Vo+mJqll7xNKs92lLyojUXISrGkID4RbWQalzsk5DWDicv1QbO8KajW@vger.kernel.org, AJvYcCX5bGeftv+ZVxEvNRGwEOSN7dLgxx/dgn0xqs1wTXgCrqSWwmUw6bf25x1UhOy4G5Tq0FuNDJ802AWemVjOkiLNGjY=@vger.kernel.org X-Received: by 2002:a05:690c:94:b0:6db:db27:24a3 with SMTP id 00721157ae682-6e2c72833eamr19404947b3.31.1728026034217; Fri, 04 Oct 2024 00:13:54 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240901183422.31600-1-biju.das.jz@bp.renesas.com> <20240901183422.31600-2-biju.das.jz@bp.renesas.com> In-Reply-To: <20240901183422.31600-2-biju.das.jz@bp.renesas.com> From: Geert Uytterhoeven Date: Fri, 4 Oct 2024 09:13:41 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 1/2] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash To: Biju Das Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar Mahadev Lad , Biju Das Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Biju, On Sun, Sep 1, 2024 at 8:34=E2=80=AFPM Biju Das wrote: > Enable Renesas at25ql128a flash connected to QSPI0. Also disable > the node from rzfive-smarc-som as it is untested. > > Tested the flash by flashing bootloaders: > flash_erase /dev/mtd0 0 0 > flash_erase /dev/mtd1 0 0 > mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE} > mtd_debug write /dev/mtd1 512 ${FIP_FILE_SIZE} ${FIP_IMAGE} > > Signed-off-by: Biju Das > --- > v3->v4: > * Updated commit description. > * Updated partition table. Thanks for the update! > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > @@ -201,6 +201,12 @@ irq { > }; > }; > > + qspi0_pins: qspi0 { > + pins =3D "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO= 3", > + "QSPI0_SPCLK", "QSPI0_SSL"; > + power-source =3D <1800>; > + }; > + > sdhi0_emmc_pins: sd0emmc { > sd0_emmc_data { > pins =3D "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "= SD0_DATA3", > @@ -252,6 +258,45 @@ sd0_mux_uhs { > }; > }; > > +&sbc { > + pinctrl-0 =3D <&qspi0_pins>; > + pinctrl-names =3D "default"; > + status =3D "okay"; > + > + flash@0 { > + compatible =3D "jedec,spi-nor"; > + reg =3D <0>; > + spi-max-frequency =3D <50000000>; > + spi-tx-bus-width =3D <4>; > + spi-rx-bus-width =3D <4>; > + > + spi-cpol; > + spi-cpha; > + m25p,fast-read; > + > + partitions { > + compatible =3D "fixed-partitions"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + > + partition@0 { > + label =3D "bl2"; > + reg =3D <0x00000000 0x0001c000>; > + }; > + > + partition@1d000 { /* fip is at offset 0x200 */ Is this 4 KiB gap between the two partitions intentional? If yes, I think it deserves a comment. > + label =3D "fip"; > + reg =3D <0x0001d000 0x7e3000>; > + }; > + > + partition@800000 { > + label =3D "user"; > + reg =3D <0x800000 0x800000>; > + }; > + }; > + }; > +}; The rest LGTM. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds