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[209.85.219.170]) by smtp.gmail.com with ESMTPSA id l9-20020a37f909000000b006b59eacba61sm1264221qkj.75.2022.07.21.04.43.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jul 2022 04:43:31 -0700 (PDT) Received: by mail-yb1-f170.google.com with SMTP id c131so2291420ybf.9; Thu, 21 Jul 2022 04:43:30 -0700 (PDT) X-Received: by 2002:a5b:6c1:0:b0:669:a7c3:4c33 with SMTP id r1-20020a5b06c1000000b00669a7c34c33mr38974765ybq.543.1658403810731; Thu, 21 Jul 2022 04:43:30 -0700 (PDT) MIME-Version: 1.0 References: <20220718195651.7711-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220718195651.7711-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Thu, 21 Jul 2022 13:43:19 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/5] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} To: "Lad, Prabhakar" Cc: Lad Prabhakar , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Prabhakar, On Thu, Jul 21, 2022 at 1:07 PM Lad, Prabhakar wrote: > On Thu, Jul 21, 2022 at 11:47 AM Geert Uytterhoeven > wrote: > > On Mon, Jul 18, 2022 at 9:57 PM Lad Prabhakar > > wrote: > > > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > > > and ETH1 respectively. > > > > > > Signed-off-by: Lad Prabhakar > > > > Thanks for your patch! > > > > > --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi > > > @@ -94,6 +94,8 @@ phy0: ethernet-phy@7 { > > > compatible = "ethernet-phy-id0022.1640", > > > "ethernet-phy-ieee802.3-c22"; > > > reg = <7>; > > > + interrupt-parent = <&irqc>; > > > + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; > > > > 2? > > > IRQ2 = SPI 3, the driver expects the SPI number and is used as index > [0] to map the interrupt in the GIC. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/irqchip/irq-renesas-rzg2l.c?h=next-20220720#n291 Using the SPI number sounds strange to me, as the consumer (Ethernet PHY) is linked to the IRQC, not to the GIC directly. > > "The first cell should contain external interrupt number (IRQ0-7)" > > > Probably I need to reword this to "The first cell should contain the > SPI number for IRQ0-7/NMI interrupt lines" ? Oh, so zero is the NMI? And 1-8 are IRQ0-7. All of this should be documented in the bindings. Probably you want to document the parent interrupts: - First entry is NMI, - Next 8 entries are IRQ0-7, - Next 32 entries are TINT0-31. Currently it's a flat list. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds