* [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support
@ 2016-09-16 13:26 Sergei Shtylyov
2016-09-16 13:28 ` [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros Sergei Shtylyov
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Sergei Shtylyov @ 2016-09-16 13:26 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Hello.
Here's the set of 8 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20160916-v4.8-rc6' tag. I'm adding the device tree support for
the R8A7743-based SK-RZG1M board. The SoC is close to R8A7791 and the board
seems identical to the R8A7791/Porter board. Only serial console is supported
for now, no DHCP/NFS support yet, it will be done RSN... :-)
[1/8] ARM: shmobile: r8a7743: add clock index macros
[2/8] ARM: shmobile: r8a7743: add power domain index macros
[3/8] soc: renesas: rcar-sysc: add R8A7743 support
[4/8] ARM: shmobile: r8a7743: basic SoC support
[5/8] ARM: dts: r8a7743: initial SoC device tree
[6/8] ARM: dts: r8a7743: add SYS-DMAC support
[7/8] ARM: dts: r8a7743: add [H]SCIF support
[8/8] ARM: dts: sk-rzg1m: initial device tree
WBR, Sergei
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros 2016-09-16 13:26 [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support Sergei Shtylyov @ 2016-09-16 13:28 ` Sergei Shtylyov 2016-09-17 10:15 ` Sergei Shtylyov [not found] ` <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:28 UTC (permalink / raw) To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree; +Cc: magnus.damm Add macros usable by the device tree sources to reference the R8A7743 clocks by index. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- include/dt-bindings/clock/r8a7743-clock.h | 157 ++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) Index: renesas/include/dt-bindings/clock/r8a7743-clock.h =================================================================== --- /dev/null +++ renesas/include/dt-bindings/clock/r8a7743-clock.h @@ -0,0 +1,157 @@ +/* + * Copyright 2013 Ideas On Board SPRL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7743_H__ +#define __DT_BINDINGS_CLOCK_R8A7743_H__ + +/* CPG */ +#define R8A7743_CLK_MAIN 0 +#define R8A7743_CLK_PLL0 1 +#define R8A7743_CLK_PLL1 2 +#define R8A7743_CLK_PLL3 3 +#define R8A7743_CLK_LB 4 +#define R8A7743_CLK_QSPI 5 +#define R8A7743_CLK_SDH 6 +#define R8A7743_CLK_SD0 7 +#define R8A7743_CLK_Z 8 +#define R8A7743_CLK_RCAN 9 + +/* MSTP0 */ +#define R8A7743_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7743_CLK_VCP0 1 +#define R8A7743_CLK_VPC0 3 +#define R8A7743_CLK_TMU1 11 +#define R8A7743_CLK_3DG 12 +#define R8A7743_CLK_2DDMAC 15 +#define R8A7743_CLK_FDP1_1 18 +#define R8A7743_CLK_FDP1_0 19 +#define R8A7743_CLK_TMU3 21 +#define R8A7743_CLK_TMU2 22 +#define R8A7743_CLK_CMT0 24 +#define R8A7743_CLK_TMU0 25 +#define R8A7743_CLK_VSP1_DU1 27 +#define R8A7743_CLK_VSP1_DU0 28 +#define R8A7743_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7743_CLK_SCIFA2 2 +#define R8A7743_CLK_SCIFA1 3 +#define R8A7743_CLK_SCIFA0 4 +#define R8A7743_CLK_MSIOF2 5 +#define R8A7743_CLK_SCIFB0 6 +#define R8A7743_CLK_SCIFB1 7 +#define R8A7743_CLK_MSIOF1 8 +#define R8A7743_CLK_SCIFB2 16 +#define R8A7743_CLK_SYS_DMAC1 18 +#define R8A7743_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7743_CLK_TPU0 4 +#define R8A7743_CLK_SDHI2 11 +#define R8A7743_CLK_SDHI1 12 +#define R8A7743_CLK_SDHI0 14 +#define R8A7743_CLK_MMCIF0 15 +#define R8A7743_CLK_IIC0 18 +#define R8A7743_CLK_PCIEC 19 +#define R8A7743_CLK_IIC1 23 +#define R8A7743_CLK_SSUSB 28 +#define R8A7743_CLK_CMT1 29 +#define R8A7743_CLK_USBDMAC0 30 +#define R8A7743_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7743_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7743_CLK_AUDIO_DMAC1 1 +#define R8A7743_CLK_AUDIO_DMAC0 2 +#define R8A7743_CLK_THERMAL 22 +#define R8A7743_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7743_CLK_EHCI 3 +#define R8A7743_CLK_HSUSB 4 +#define R8A7743_CLK_HSCIF2 13 +#define R8A7743_CLK_SCIF5 14 +#define R8A7743_CLK_SCIF4 15 +#define R8A7743_CLK_HSCIF1 16 +#define R8A7743_CLK_HSCIF0 17 +#define R8A7743_CLK_SCIF3 18 +#define R8A7743_CLK_SCIF2 19 +#define R8A7743_CLK_SCIF1 20 +#define R8A7743_CLK_SCIF0 21 +#define R8A7743_CLK_DU1 23 +#define R8A7743_CLK_DU0 24 +#define R8A7743_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7743_CLK_IPMMU_SGX 0 +#define R8A7743_CLK_VIN2 9 +#define R8A7743_CLK_VIN1 10 +#define R8A7743_CLK_VIN0 11 +#define R8A7743_CLK_ETHER 13 +#define R8A7743_CLK_SATA1 14 +#define R8A7743_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7743_CLK_GPIO7 4 +#define R8A7743_CLK_GPIO6 5 +#define R8A7743_CLK_GPIO5 7 +#define R8A7743_CLK_GPIO4 8 +#define R8A7743_CLK_GPIO3 9 +#define R8A7743_CLK_GPIO2 10 +#define R8A7743_CLK_GPIO1 11 +#define R8A7743_CLK_GPIO0 12 +#define R8A7743_CLK_RCAN1 15 +#define R8A7743_CLK_RCAN0 16 +#define R8A7743_CLK_QSPI_MOD 17 +#define R8A7743_CLK_I2C5 25 +#define R8A7743_CLK_IICDVFS 26 +#define R8A7743_CLK_I2C4 27 +#define R8A7743_CLK_I2C3 28 +#define R8A7743_CLK_I2C2 29 +#define R8A7743_CLK_I2C1 30 +#define R8A7743_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7743_CLK_SSI_ALL 5 +#define R8A7743_CLK_SSI9 6 +#define R8A7743_CLK_SSI8 7 +#define R8A7743_CLK_SSI7 8 +#define R8A7743_CLK_SSI6 9 +#define R8A7743_CLK_SSI5 10 +#define R8A7743_CLK_SSI4 11 +#define R8A7743_CLK_SSI3 12 +#define R8A7743_CLK_SSI2 13 +#define R8A7743_CLK_SSI1 14 +#define R8A7743_CLK_SSI0 15 +#define R8A7743_CLK_SCU_ALL 17 +#define R8A7743_CLK_SCU_DVC1 18 +#define R8A7743_CLK_SCU_DVC0 19 +#define R8A7743_CLK_SCU_CTU1_MIX1 20 +#define R8A7743_CLK_SCU_CTU0_MIX0 21 +#define R8A7743_CLK_SCU_SRC9 22 +#define R8A7743_CLK_SCU_SRC8 23 +#define R8A7743_CLK_SCU_SRC7 24 +#define R8A7743_CLK_SCU_SRC6 25 +#define R8A7743_CLK_SCU_SRC5 26 +#define R8A7743_CLK_SCU_SRC4 27 +#define R8A7743_CLK_SCU_SRC3 28 +#define R8A7743_CLK_SCU_SRC2 29 +#define R8A7743_CLK_SCU_SRC1 30 +#define R8A7743_CLK_SCU_SRC0 31 + +/* MSTP11 */ +#define R8A7743_CLK_SCIFA3 6 +#define R8A7743_CLK_SCIFA4 7 +#define R8A7743_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7743_H__ */ ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros 2016-09-16 13:28 ` [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros Sergei Shtylyov @ 2016-09-17 10:15 ` Sergei Shtylyov 0 siblings, 0 replies; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-17 10:15 UTC (permalink / raw) To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree; +Cc: magnus.damm On 9/16/2016 4:28 PM, Sergei Shtylyov wrote: > Add macros usable by the device tree sources to reference the R8A7743 > clocks by index. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > include/dt-bindings/clock/r8a7743-clock.h | 157 ++++++++++++++++++++++++++++++ > 1 file changed, 157 insertions(+) > > Index: renesas/include/dt-bindings/clock/r8a7743-clock.h > =================================================================== > --- /dev/null > +++ renesas/include/dt-bindings/clock/r8a7743-clock.h > @@ -0,0 +1,157 @@ > +/* > + * Copyright 2013 Ideas On Board SPRL Sorry, stupid copy/paste mistake, should have Cogent's copyright. Will re-spin soon... MBR, Sergei ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>]
* [PATCH RFC 2/8] ARM: shmobile: r8a7743: add power domain index macros [not found] ` <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> @ 2016-09-16 13:29 ` Sergei Shtylyov [not found] ` <2361310.TQ5AHhpEmD-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> 2016-09-16 13:37 ` [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support Sergei Shtylyov 1 sibling, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:29 UTC (permalink / raw) To: horms-/R6kz+dDXgpPR4JQBCEnsQ, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w Add macros usable by the device tree sources to reference R8A7743 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> --- include/dt-bindings/power/r8a7743-sysc.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) Index: renesas/include/dt-bindings/power/r8a7743-sysc.h =================================================================== --- /dev/null +++ renesas/include/dt-bindings/power/r8a7743-sysc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7743_PD_CA15_CPU0 0 +#define R8A7743_PD_CA15_CPU1 1 +#define R8A7743_PD_CA15_SCU 12 +#define R8A7743_PD_SGX 20 + +/* Always-on power area */ +#define R8A7743_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */ -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <2361310.TQ5AHhpEmD-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH RFC 2/8] ARM: shmobile: r8a7743: add power domain index macros [not found] ` <2361310.TQ5AHhpEmD-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> @ 2016-09-19 7:46 ` Geert Uytterhoeven 0 siblings, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 7:46 UTC (permalink / raw) To: Sergei Shtylyov Cc: Simon Horman, Linux-Renesas, Rob Herring, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Magnus Damm On Fri, Sep 16, 2016 at 3:29 PM, Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> wrote: > Add macros usable by the device tree sources to reference R8A7743 SYSC power > domains by index. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support [not found] ` <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> 2016-09-16 13:29 ` [PATCH RFC 2/8] ARM: shmobile: r8a7743: add power domain " Sergei Shtylyov @ 2016-09-16 13:37 ` Sergei Shtylyov 2016-09-19 8:32 ` Geert Uytterhoeven 1 sibling, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:37 UTC (permalink / raw) To: horms-/R6kz+dDXgpPR4JQBCEnsQ, linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w, linux-lFZ/pmaqli7XmaaqVzeoHQ, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Describe [H]SCIFs in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> --- arch/arm/boot/dts/r8a7743.dtsi | 262 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 262 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -154,6 +154,268 @@ dma-channels = <15>; }; + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA1>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFA2>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA3>; + clock-names = "fck"; + dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA4>; + clock-names = "fck"; + dmas = <&dmac0 0x1f>, <&dmac0 0x20>, + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7743", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7743_CLK_SCIFA5>; + clock-names = "fck"; + dmas = <&dmac0 0x23>, <&dmac0 0x24>, + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 64>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB0>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 64>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB1>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7743", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 64>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7743_CLK_SCIFB2>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF3>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2f>, <&dmac0 0x30>, + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF4>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7743", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_SCIF5>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF0>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF1>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7743", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7743_CLK_HSCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7743-cpg-clocks", -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support 2016-09-16 13:37 ` [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support Sergei Shtylyov @ 2016-09-19 8:32 ` Geert Uytterhoeven 0 siblings, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 8:32 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, devicetree@vger.kernel.org, Russell King, Magnus Damm, Rob Herring, Linux-Renesas, Simon Horman, linux-arm-kernel@lists.infradead.org Hi Sergei, On Fri, Sep 16, 2016 at 3:37 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe [H]SCIFs in the R8A7743 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi > +++ renesas/arch/arm/boot/dts/r8a7743.dtsi > @@ -154,6 +154,268 @@ > dma-channels = <15>; > }; > > + scifa0: serial@e6c40000 { > + compatible = "renesas,scifa-r8a7743", To be documented... > + "renesas,rcar-gen2-scifa", "renesas,scifa"; > + reg = <0 0xe6c40000 0 64>; > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>; > + clock-names = "fck"; > + dmas = <&dmac0 0x21>, <&dmac0 0x22>, > + <&dmac1 0x21>, <&dmac1 0x22>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; > + status = "disabled"; > + }; [...] > + scifb0: serial@e6c20000 { > + compatible = "renesas,scifb-r8a7743", To be documented... > + "renesas,rcar-gen2-scifb", "renesas,scifb"; > + reg = <0 0xe6c20000 0 64>; This does not cover the whole register block (aha, also on existing Gen2). "reg = <0 0xe6c20000 0 256>;"? > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp2_clks R8A7743_CLK_SCIFB0>; > + clock-names = "fck"; > + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, > + <&dmac1 0x3d>, <&dmac1 0x3e>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; > + status = "disabled"; > + }; [...] > + scif0: serial@e6e60000 { > + compatible = "renesas,scif-r8a7743", To be documented... > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6e60000 0 64>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp7_clks R8A7743_CLK_SCIF0>, <&zs_clk>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, > + <&dmac1 0x29>, <&dmac1 0x2a>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; > + status = "disabled"; > + }; > + > + scif1: serial@e6e68000 { > + compatible = "renesas,scif-r8a7743", > + "renesas,rcar-gen2-scif", "renesas,scif"; > + reg = <0 0xe6e68000 0 64>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp7_clks R8A7743_CLK_SCIF1>, <&zs_clk>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, > + <&dmac1 0x2d>, <&dmac1 0x2e>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; > + status = "disabled"; > + }; [...] > + hscif0: serial@e62c0000 { > + compatible = "renesas,hscif-r8a7743", To be documented... > + "renesas,rcar-gen2-hscif", "renesas,hscif"; > + reg = <0 0xe62c0000 0 96>; > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&mstp7_clks R8A7743_CLK_HSCIF0>, <&zs_clk>, > + <&scif_clk>; > + clock-names = "fck", "brg_int", "scif_clk"; > + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, > + <&dmac1 0x39>, <&dmac1 0x3a>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; > + status = "disabled"; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree 2016-09-16 13:26 [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support Sergei Shtylyov 2016-09-16 13:28 ` [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros Sergei Shtylyov [not found] ` <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org> @ 2016-09-16 13:35 ` Sergei Shtylyov 2016-09-19 8:14 ` Geert Uytterhoeven 2016-09-16 13:36 ` [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov 2016-09-16 13:38 ` [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov 4 siblings, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:35 UTC (permalink / raw) To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree Cc: magnus.damm, linux, linux-arm-kernel The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7743.dtsi | 210 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,210 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a7743-clock.h> +#include <dt-bindings/power/r8a7743-sysc.h> + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg_clocks R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1500000000>; + power-domains = <&sysc R8A7743_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7743-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk &usb_extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan"; + #power-domain-cells = <0>; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + zs_clk: zs { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + }; + p_clk: p { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7743_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + }; + mp_clk: mp { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + }; + + /* Gate clocks */ + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_SCIFA2 R8A7743_CLK_SCIFA1 + R8A7743_CLK_SCIFA0 R8A7743_CLK_SCIFB0 + R8A7743_CLK_SCIFB1 R8A7743_CLK_SCIFB2 + R8A7743_CLK_SYS_DMAC1 R8A7743_CLK_SYS_DMAC0 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", + "scifb0", "scifb1", "scifb2", + "sys-dmac1", "sys-dmac0"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_HSCIF2 R8A7743_CLK_SCIF5 + R8A7743_CLK_SCIF4 R8A7743_CLK_HSCIF1 + R8A7743_CLK_HSCIF0 R8A7743_CLK_SCIF3 + R8A7743_CLK_SCIF2 R8A7743_CLK_SCIF1 + R8A7743_CLK_SCIF0 + >; + clock-output-names = + "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7743-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7743_CLK_SCIFA3 R8A7743_CLK_SCIFA4 + R8A7743_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +}; ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree 2016-09-16 13:35 ` [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov @ 2016-09-19 8:14 ` Geert Uytterhoeven 0 siblings, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 8:14 UTC (permalink / raw) To: Sergei Shtylyov Cc: Simon Horman, Linux-Renesas, Rob Herring, Mark Rutland, devicetree@vger.kernel.org, Magnus Damm, Russell King, linux-arm-kernel@lists.infradead.org Hi Sergei, On Fri, Sep 16, 2016 at 3:35 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > The initial R8A7743 SoC device tree including CPU cores, GIC, timer, SYSC, > and the required clock descriptions. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > --- /dev/null/ > +++ renesas/arch/arm/boot/dts/r8a7743.dtsi > @@ -0,0 +1,210 @@ > +/ { > + soc { = > + /* Special CPG clocks */ > + cpg_clocks: cpg_clocks@e6150000 { > + compatible = "renesas,r8a7743-cpg-clocks", > + "renesas,rcar-gen2-cpg-clocks"; For a new SoC family, I would strongly suggest using a renesas,cpg-mssr based binding instead: - No more mstp*_clocks nodes with array triplets to keep in sync, - Support for MSSR reset can be added later, - No need to add all those fixed-factor clocks to DT, - Less DT churn when adding support for new devices. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support 2016-09-16 13:26 [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (2 preceding siblings ...) 2016-09-16 13:35 ` [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov @ 2016-09-16 13:36 ` Sergei Shtylyov 2016-09-19 8:18 ` Geert Uytterhoeven 2016-09-19 8:19 ` Geert Uytterhoeven 2016-09-16 13:38 ` [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov 4 siblings, 2 replies; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:36 UTC (permalink / raw) To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree Cc: magnus.damm, linux, linux-arm-kernel Describe SYS-DMAC0/1 in the R8A7743 device tree. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/r8a7743.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -90,6 +90,70 @@ #power-domain-cells = <1>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC0>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7743", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC1>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #dma-cells = <1>; + dma-channels = <15>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7743-cpg-clocks", ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support 2016-09-16 13:36 ` [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov @ 2016-09-19 8:18 ` Geert Uytterhoeven 2016-09-19 8:19 ` Geert Uytterhoeven 1 sibling, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 8:18 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, devicetree@vger.kernel.org, Russell King, Magnus Damm, Rob Herring, Linux-Renesas, Simon Horman, linux-arm-kernel@lists.infradead.org On Fri, Sep 16, 2016 at 3:36 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe SYS-DMAC0/1 in the R8A7743 device tree. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> (but the clocks properties will have to be changed due to CPG/MSSR) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support 2016-09-16 13:36 ` [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov 2016-09-19 8:18 ` Geert Uytterhoeven @ 2016-09-19 8:19 ` Geert Uytterhoeven 2016-09-28 20:09 ` Sergei Shtylyov 1 sibling, 1 reply; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 8:19 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, devicetree@vger.kernel.org, Russell King, Magnus Damm, Rob Herring, Linux-Renesas, Simon Horman, linux-arm-kernel@lists.infradead.org On Fri, Sep 16, 2016 at 3:36 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi > +++ renesas/arch/arm/boot/dts/r8a7743.dtsi > @@ -90,6 +90,70 @@ > #power-domain-cells = <1>; > }; > > + dmac0: dma-controller@e6700000 { > + compatible = "renesas,dmac-r8a7743", To be documented. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support 2016-09-19 8:19 ` Geert Uytterhoeven @ 2016-09-28 20:09 ` Sergei Shtylyov [not found] ` <be7575a5-e9a0-05a6-5b2d-803632c7edac-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> 0 siblings, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-28 20:09 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Simon Horman, Linux-Renesas, Rob Herring, Mark Rutland, devicetree@vger.kernel.org, Magnus Damm, Russell King, linux-arm-kernel@lists.infradead.org On 09/19/2016 11:19 AM, Geert Uytterhoeven wrote: >> --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi >> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi >> @@ -90,6 +90,70 @@ >> #power-domain-cells = <1>; >> }; >> >> + dmac0: dma-controller@e6700000 { >> + compatible = "renesas,dmac-r8a7743", > > To be documented. The R-Car DMAC binding has "renesas,dmac-<soctype>" documented. I can add the mention of RZ/G and new examples though... > Gr{oetje,eeting}s, > > Geert MBR, Sergei ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <be7575a5-e9a0-05a6-5b2d-803632c7edac-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>]
* Re: [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support [not found] ` <be7575a5-e9a0-05a6-5b2d-803632c7edac-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> @ 2016-09-29 6:36 ` Geert Uytterhoeven 0 siblings, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-29 6:36 UTC (permalink / raw) To: Sergei Shtylyov Cc: Simon Horman, Linux-Renesas, Rob Herring, Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Magnus Damm, Russell King, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Hi Sergei, On Wed, Sep 28, 2016 at 10:09 PM, Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> wrote: > On 09/19/2016 11:19 AM, Geert Uytterhoeven wrote: >>> --- renesas.orig/arch/arm/boot/dts/r8a7743.dtsi >>> +++ renesas/arch/arm/boot/dts/r8a7743.dtsi >>> @@ -90,6 +90,70 @@ >>> #power-domain-cells = <1>; >>> }; >>> >>> + dmac0: dma-controller@e6700000 { >>> + compatible = "renesas,dmac-r8a7743", >> >> >> To be documented. > > The R-Car DMAC binding has "renesas,dmac-<soctype>" documented. > I can add the mention of RZ/G and new examples though... Just adding a line for RZ/G1M should be sufficient. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree 2016-09-16 13:26 [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support Sergei Shtylyov ` (3 preceding siblings ...) 2016-09-16 13:36 ` [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov @ 2016-09-16 13:38 ` Sergei Shtylyov 2016-09-19 8:42 ` Geert Uytterhoeven 4 siblings, 1 reply; 16+ messages in thread From: Sergei Shtylyov @ 2016-09-16 13:38 UTC (permalink / raw) To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree Cc: magnus.damm, linux, linux-arm-kernel Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. The board has one debug serial port (SCIF0); include support for it, so that the serial console can work. Based on the original (and large) patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/boot/dts/Makefile | 1 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) Index: renesas/arch/arm/boot/dts/Makefile =================================================================== --- renesas.orig/arch/arm/boot/dts/Makefile +++ renesas/arch/arm/boot/dts/Makefile @@ -654,6 +654,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ + r8a7743-sk-rzg1m.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ r8a7790-lager.dtb \ Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts @@ -0,0 +1,44 @@ +/* + * Device Tree Source for the SK-RZG1M board + * + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7743.dtsi" + +/ { + model = "SK-RZG1M"; + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&scif0 { + status = "okay"; +}; ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree 2016-09-16 13:38 ` [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov @ 2016-09-19 8:42 ` Geert Uytterhoeven 0 siblings, 0 replies; 16+ messages in thread From: Geert Uytterhoeven @ 2016-09-19 8:42 UTC (permalink / raw) To: Sergei Shtylyov Cc: Mark Rutland, devicetree@vger.kernel.org, Russell King, Magnus Damm, Rob Herring, Linux-Renesas, Simon Horman, linux-arm-kernel@lists.infradead.org On Fri, Sep 16, 2016 at 3:38 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Add the initial device tree for the R8A7743 SoC based SK-RZG1M board. > The board has one debug serial port (SCIF0); include support for it, so > that the serial console can work. > > Based on the original (and large) patch by Dmitry Shifrin > <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- /dev/null > +++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts > @@ -0,0 +1,44 @@ > + compatible = "renesas,sk-rzg1m", "renesas,r8a7743"; To be documented in Documentation/devicetree/bindings/arm/shmobile.txt Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-09-29 6:36 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2016-09-16 13:26 [PATCH RFC 0/8] Add R8A7743/SK-RZG1M board support Sergei Shtylyov
2016-09-16 13:28 ` [PATCH RFC 1/8] ARM: shmobile: r8a7743: add clock index macros Sergei Shtylyov
2016-09-17 10:15 ` Sergei Shtylyov
[not found] ` <3533019.Wim1Kuh1ic-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-09-16 13:29 ` [PATCH RFC 2/8] ARM: shmobile: r8a7743: add power domain " Sergei Shtylyov
[not found] ` <2361310.TQ5AHhpEmD-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>
2016-09-19 7:46 ` Geert Uytterhoeven
2016-09-16 13:37 ` [PATCH RFC 7/8] ARM: dts: r8a7743: add [H]SCIF support Sergei Shtylyov
2016-09-19 8:32 ` Geert Uytterhoeven
2016-09-16 13:35 ` [PATCH RFC 5/8] ARM: dts: r8a7743: initial SoC device tree Sergei Shtylyov
2016-09-19 8:14 ` Geert Uytterhoeven
2016-09-16 13:36 ` [PATCH RFC 6/8] ARM: dts: r8a7743: add SYS-DMAC support Sergei Shtylyov
2016-09-19 8:18 ` Geert Uytterhoeven
2016-09-19 8:19 ` Geert Uytterhoeven
2016-09-28 20:09 ` Sergei Shtylyov
[not found] ` <be7575a5-e9a0-05a6-5b2d-803632c7edac-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
2016-09-29 6:36 ` Geert Uytterhoeven
2016-09-16 13:38 ` [PATCH RFC 8/8] ARM: dts: sk-rzg1m: initial device tree Sergei Shtylyov
2016-09-19 8:42 ` Geert Uytterhoeven
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