From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49FB1C433FE for ; Wed, 23 Feb 2022 12:54:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240642AbiBWMzB (ORCPT ); Wed, 23 Feb 2022 07:55:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240648AbiBWMzA (ORCPT ); Wed, 23 Feb 2022 07:55:00 -0500 Received: from mail-vk1-f170.google.com (mail-vk1-f170.google.com [209.85.221.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E7DF9858D; Wed, 23 Feb 2022 04:54:33 -0800 (PST) Received: by mail-vk1-f170.google.com with SMTP id x62so4384650vkg.6; Wed, 23 Feb 2022 04:54:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=j2ZMGyGypWkGWFhVkz7FZ46Wu3326iiOknUbX8FkqQc=; b=1kGO+j6XIkGyzJduHrUxwiE7xPJaIY68FWw3YQYArI+Ct5I00T/jlehhrPO99c6tLz l0pwhuxPCkNzUtXv6MMZRVxZmfB0MEDgAFgiYBrU7x04TSnpO8RFNc59xk4hGZw/xQU5 ADXkYKrjqk1ahL0bCmeG2cRBBUi5wmutaQK0e06ARHhUGVYj0gMh6KTbV/jgEFH92rY7 IaTkvL3QqA80gTTEdr++R8+eRfF/42Vw7G3Mwxbr+Tl46Il0pgq/TOZbww8I05ZT/OUK TLDGzEBXZX6J5g2lzc3BBQb+YTbQvL5B6OMoEo9sJAqTTzb1+F3HzboFE0reATrgtQEl 5bZg== X-Gm-Message-State: AOAM533MWgjeCeAA4AZxGEygmqJXcboDTI9XVQeVeZ/05xEG4Fv86MMf 0okTmwqPoWGpbCHk2r/+UeCKa/F8fV6b9w== X-Google-Smtp-Source: ABdhPJz70u6fKHBVE1l4VulJrXlA8Oh3E59jKSdnBca6ZnSC4P+j20s20M1Qcpkt5c1FXlBBCBbeKQ== X-Received: by 2002:a1f:6087:0:b0:328:e94a:54b3 with SMTP id u129-20020a1f6087000000b00328e94a54b3mr12317218vkb.20.1645620872480; Wed, 23 Feb 2022 04:54:32 -0800 (PST) Received: from mail-vs1-f43.google.com (mail-vs1-f43.google.com. [209.85.217.43]) by smtp.gmail.com with ESMTPSA id y5sm680559vsj.11.2022.02.23.04.54.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Feb 2022 04:54:32 -0800 (PST) Received: by mail-vs1-f43.google.com with SMTP id t22so3036748vsa.4; Wed, 23 Feb 2022 04:54:32 -0800 (PST) X-Received: by 2002:a67:af08:0:b0:31b:9451:bc39 with SMTP id v8-20020a67af08000000b0031b9451bc39mr12147208vsl.68.1645620871857; Wed, 23 Feb 2022 04:54:31 -0800 (PST) MIME-Version: 1.0 References: <20220222103437.194779-1-miquel.raynal@bootlin.com> <20220222103437.194779-8-miquel.raynal@bootlin.com> In-Reply-To: <20220222103437.194779-8-miquel.raynal@bootlin.com> From: Geert Uytterhoeven Date: Wed, 23 Feb 2022 13:54:20 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 7/8] ARM: dts: r9a06g032: Add the two DMA nodes To: Miquel Raynal Cc: Vinod Koul , Andy Shevchenko , dmaengine , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux-Renesas , Magnus Damm , Gareth Williams , Phil Edworthy , Stephen Boyd , Michael Turquette , linux-clk , Thomas Petazzoni , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Miquel, On Tue, Feb 22, 2022 at 11:35 AM Miquel Raynal wrote: > Describe the two DMA controllers available on this SoC. > > Signed-off-by: Miquel Raynal Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -184,6 +184,36 @@ nand_controller: nand-controller@40102000 { > status = "disabled"; > }; > > + dma0: dma-controller@40104000 { > + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; > + reg = <0x40104000 0x1000>; > + interrupts = ; > + clock-names = "hclk"; > + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; power-domains? > + dma-channels = <8>; > + dma-requests = <16>; > + dma-masters = <1>; > + #dma-cells = <3>; <4>? The dmamux bindings say: + The first four cells are dedicated to the master DMA controller. The fifth + cell gives the DMA mux bit index that must be set starting from 0. The + sixth cell gives the binary value that must be written there, ie. 0 or 1. > + block_size = <0xfff>; > + data_width = <3>; > + status = "disabled"; > + }; The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds