* [PATCH 0/2] Add CPG wrapper for Renesas RZ/Five SoC
@ 2022-06-22 18:17 Lad Prabhakar
2022-06-22 18:17 ` [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar
2022-06-22 18:17 ` [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC Lad Prabhakar
0 siblings, 2 replies; 6+ messages in thread
From: Lad Prabhakar @ 2022-06-22 18:17 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, linux-renesas-soc, linux-clk, devicetree
Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
Hi All,
This patch series adds CPG wrapper for Renesas RZ/Five SoC. RZ/Five SoC
has almost identical clock structure compared to RZ/G2UL, so
r9a07g043-cpg.c file is re-used to add support for Renesas RZ/Five SoC.
Below is the clock structure reported by Linux with this patch series:
/ # cat /sys/devices/soc0/family
RZ/Five
/ # cat /sys/devices/soc0/machine
Renesas SMARC EVK based on r9a07g043
/ # cat /sys/devices/soc0/revision
0
/ # cat /sys/devices/soc0/soc_id
r9a07g043
/ #
/ # cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
extal 3 3 0 24000000 0 0 50000 Y
.pll6 0 0 0 500000000 0 0 50000 Y
.pll6_250 0 0 0 250000000 0 0 50000 Y
HP 0 0 0 250000000 0 0 50000 Y
.pll3 1 1 0 1600000000 0 0 50000 Y
.pll3_533 0 0 0 533333333 0 0 50000 Y
.sel_pll3_3 0 0 0 533333333 0 0 50000 Y
divpl3c 0 0 0 266666667 0 0 50000 Y
SPI1 0 0 0 66666666 0 0 50000 Y
spi_clk2 0 0 0 66666666 0 0 50000 N
SPI0 0 0 0 133333333 0 0 50000 Y
spi_clk 0 0 0 133333333 0 0 50000 N
.pll3_400 0 0 0 400000000 0 0 50000 Y
.pll3_div2 1 1 0 800000000 0 0 50000 Y
.pll3_div2_4 1 1 0 200000000 0 0 50000 Y
M0 0 0 0 200000000 0 0 50000 Y
eth1_axi 0 0 0 200000000 0 0 50000 N
eth0_axi 0 0 0 200000000 0 0 50000 N
P1 3 3 0 200000000 0 0 50000 Y
usb_pclk 0 0 0 200000000 0 0 50000 N
usb0_func 0 0 0 200000000 0 0 50000 N
usb1_host 0 0 0 200000000 0 0 50000 N
usb0_host 0 0 0 200000000 0 0 50000 N
sdhi1_aclk 0 0 0 200000000 0 0 50000 N
sdhi0_aclk 0 0 0 200000000 0 0 50000 N
dmac_aclk 2 2 0 200000000 0 0 50000 Y
iax45_clk 1 1 0 200000000 0 0 50000 Y
P1_DIV2 1 1 0 100000000 0 0 50000 Y
dmac_pclk 1 1 0 100000000 0 0 50000 Y
.pll3_div2_4_2 0 0 0 100000000 0 0 50000 Y
ZT 0 0 0 100000000 0 0 50000 Y
eth1_chi 0 0 0 100000000 0 0 50000 N
eth0_chi 0 0 0 100000000 0 0 50000 N
P2 0 0 0 100000000 0 0 50000 Y
iax45_pclk 0 0 0 100000000 0 0 50000 N
.pll2 1 1 0 1600000000 0 0 50000 Y
.clk_533 0 0 0 533333333 0 0 50000 Y
sd1 0 0 0 533333333 0 0 50000 Y
sdhi1_clk_hs 0 0 0 533333333 0 0 50000 N
SD1_DIV4 0 0 0 133333333 0 0 50000 Y
sdhi1_imclk2 0 0 0 133333333 0 0 50000 N
sdhi1_imclk 0 0 0 133333333 0 0 50000 N
sd0 0 0 0 533333333 0 0 50000 Y
sdhi0_clk_hs 0 0 0 533333333 0 0 50000 N
SD0_DIV4 0 0 0 133333333 0 0 50000 Y
sdhi0_imclk2 0 0 0 133333333 0 0 50000 N
sdhi0_imclk 0 0 0 133333333 0 0 50000 N
.clk_266 0 0 0 266666666 0 0 50000 Y
.clk_800 0 0 0 800000000 0 0 50000 Y
.clk_400 0 0 0 400000000 0 0 50000 Y
.pll2_div2 1 1 0 800000000 0 0 50000 Y
.pll2_div2_10 0 0 0 80000000 0 0 50000 Y
TSU 0 0 0 80000000 0 0 50000 Y
tsu_pclk 0 0 0 80000000 0 0 50000 N
adc_adclk 0 0 0 80000000 0 0 50000 N
.pll2_div2_8 1 1 0 100000000 0 0 50000 Y
P0 1 3 0 100000000 0 0 50000 Y
adc_pclk 0 0 0 100000000 0 0 50000 N
canfd 0 0 0 100000000 0 0 50000 N
rspi2 0 0 0 100000000 0 0 50000 N
rspi1 0 0 0 100000000 0 0 50000 N
rspi0 0 0 0 100000000 0 0 50000 N
sci1 0 0 0 100000000 0 0 50000 N
sci0 0 0 0 100000000 0 0 50000 N
scif4 0 0 0 100000000 0 0 50000 N
scif3 0 0 0 100000000 0 0 50000 N
scif2 0 0 0 100000000 0 0 50000 N
scif1 0 0 0 100000000 0 0 50000 N
scif0 2 2 0 100000000 0 0 50000 Y
i2c3 0 0 0 100000000 0 0 50000 N
i2c2 0 0 0 100000000 0 0 50000 N
i2c1 0 1 0 100000000 0 0 50000 N
i2c0 0 1 0 100000000 0 0 50000 N
ssi3_sfr 0 0 0 100000000 0 0 50000 N
ssi3_pclk 0 0 0 100000000 0 0 50000 N
ssi2_sfr 0 0 0 100000000 0 0 50000 N
ssi2_pclk 0 0 0 100000000 0 0 50000 N
ssi1_sfr 0 0 0 100000000 0 0 50000 N
ssi1_pclk 0 0 0 100000000 0 0 50000 N
ssi0_sfr 0 0 0 100000000 0 0 50000 N
ssi0_pclk 0 0 0 100000000 0 0 50000 N
wdt2_pclk 0 0 0 100000000 0 0 50000 N
wdt0_pclk 0 0 0 100000000 0 0 50000 N
ostm2_pclk 0 0 0 100000000 0 0 50000 N
ostm1_pclk 0 0 0 100000000 0 0 50000 N
ostm0_pclk 0 0 0 100000000 0 0 50000 N
P0_DIV2 0 0 0 50000000 0 0 50000 Y
.pll1 0 0 0 1000000000 0 0 50000 Y
I 0 0 0 1000000000 0 0 50000 Y
.osc_div1000 0 0 0 24000 0 0 50000 Y
.osc 1 1 0 24000000 0 0 50000 Y
gpio 1 2 0 24000000 0 0 50000 Y
wdt2_clk 0 0 0 24000000 0 0 50000 N
wdt0_clk 0 0 0 24000000 0 0 50000 N
/ #
/ #
/ #
RFC->v1:
* Fixed review comments pointed by Geert.
RFC: https://patchwork.ozlabs.org/project/devicetree-bindings/cover/
20220505193143.31826-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (2):
dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
Reset Definitions
clk: renesas: r9a07g043: Add support for RZ/Five SoC
drivers/clk/renesas/r9a07g043-cpg.c | 32 +++++++++++++++++++++++
include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++
2 files changed, 52 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions 2022-06-22 18:17 [PATCH 0/2] Add CPG wrapper for Renesas RZ/Five SoC Lad Prabhakar @ 2022-06-22 18:17 ` Lad Prabhakar 2022-06-23 12:05 ` Krzysztof Kozlowski 2022-06-28 9:48 ` Geert Uytterhoeven 2022-06-22 18:17 ` [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC Lad Prabhakar 1 sibling, 2 replies; 6+ messages in thread From: Lad Prabhakar @ 2022-06-22 18:17 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-renesas-soc, linux-clk, devicetree Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just amend the RZ/Five CPG clock and reset definitions. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> --- include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 27e232733096..77cde8effdc7 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -108,6 +108,15 @@ #define R9A07G043_ADC_ADCLK 76 #define R9A07G043_ADC_PCLK 77 #define R9A07G043_TSU_PCLK 78 +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ +#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ +#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ /* R9A07G043 Resets */ #define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ @@ -180,5 +189,16 @@ #define R9A07G043_ADC_PRESETN 67 #define R9A07G043_ADC_ADRST_N 68 #define R9A07G043_TSU_PRESETN 69 +#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ +#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ +#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ + #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions 2022-06-22 18:17 ` [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar @ 2022-06-23 12:05 ` Krzysztof Kozlowski 2022-06-28 9:48 ` Geert Uytterhoeven 1 sibling, 0 replies; 6+ messages in thread From: Krzysztof Kozlowski @ 2022-06-23 12:05 UTC (permalink / raw) To: Lad Prabhakar, Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-renesas-soc, linux-clk, devicetree Cc: linux-kernel, Prabhakar, Biju Das On 22/06/2022 20:17, Lad Prabhakar wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > amend the RZ/Five CPG clock and reset definitions. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions 2022-06-22 18:17 ` [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar 2022-06-23 12:05 ` Krzysztof Kozlowski @ 2022-06-28 9:48 ` Geert Uytterhoeven 1 sibling, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2022-06-28 9:48 UTC (permalink / raw) To: Lad Prabhakar Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Linux-Renesas, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar, Biju Das On Wed, Jun 22, 2022 at 8:17 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > amend the RZ/Five CPG clock and reset definitions. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Will queue in renesas-clk-for-v5.20. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC 2022-06-22 18:17 [PATCH 0/2] Add CPG wrapper for Renesas RZ/Five SoC Lad Prabhakar 2022-06-22 18:17 ` [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar @ 2022-06-22 18:17 ` Lad Prabhakar 2022-06-28 9:48 ` Geert Uytterhoeven 1 sibling, 1 reply; 6+ messages in thread From: Lad Prabhakar @ 2022-06-22 18:17 UTC (permalink / raw) To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-renesas-soc, linux-clk, devicetree Cc: linux-kernel, Prabhakar, Biju Das, Lad Prabhakar Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for RZ/Five SoC. This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g043-cpg.c | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 33c2bd8df2e5..37475465100d 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -36,9 +36,11 @@ enum clk_ids { CLK_PLL3_DIV2_4_2, CLK_SEL_PLL3_3, CLK_DIV_PLL3_C, +#ifdef CONFIG_ARM64 CLK_PLL5, CLK_PLL5_500, CLK_PLL5_250, +#endif CLK_PLL6, CLK_PLL6_250, CLK_P1_DIV2, @@ -100,9 +102,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), +#ifdef CONFIG_ARM64 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), +#endif DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), @@ -126,12 +130,20 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { }; static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { +#ifdef CONFIG_ARM64 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 0x514, 0), DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 0x518, 1), +#endif +#ifdef CONFIG_RISCV + DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, + 0x518, 0), + DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, + 0x518, 1), +#endif DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 0x52c, 0), DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, @@ -243,9 +255,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { }; static struct rzg2l_reset r9a07g043_resets[] = { +#ifdef CONFIG_ARM64 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), +#endif +#ifdef CONFIG_RISCV + DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), +#endif DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), @@ -291,8 +308,13 @@ static struct rzg2l_reset r9a07g043_resets[] = { }; static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { +#ifdef CONFIG_ARM64 MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, MOD_CLK_BASE + R9A07G043_IA55_CLK, +#endif +#ifdef CONFIG_RISCV + MOD_CLK_BASE + R9A07G043_IAX45_CLK, +#endif MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; @@ -310,11 +332,21 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = { /* Module Clocks */ .mod_clks = r9a07g043_mod_clks, .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), +#ifdef CONFIG_ARM64 .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, +#endif +#ifdef CONFIG_RISCV + .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, +#endif /* Resets */ .resets = r9a07g043_resets, +#ifdef CONFIG_ARM64 .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ +#endif +#ifdef CONFIG_RISCV + .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ +#endif .has_clk_mon_regs = true, }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC 2022-06-22 18:17 ` [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC Lad Prabhakar @ 2022-06-28 9:48 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2022-06-28 9:48 UTC (permalink / raw) To: Lad Prabhakar Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Linux-Renesas, linux-clk, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux Kernel Mailing List, Prabhakar, Biju Das On Wed, Jun 22, 2022 at 8:17 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for > RZ/Five SoC. > > This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five > SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.20. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-06-28 9:49 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-22 18:17 [PATCH 0/2] Add CPG wrapper for Renesas RZ/Five SoC Lad Prabhakar 2022-06-22 18:17 ` [PATCH 1/2] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions Lad Prabhakar 2022-06-23 12:05 ` Krzysztof Kozlowski 2022-06-28 9:48 ` Geert Uytterhoeven 2022-06-22 18:17 ` [PATCH 2/2] clk: renesas: r9a07g043: Add support for RZ/Five SoC Lad Prabhakar 2022-06-28 9:48 ` Geert Uytterhoeven
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