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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6eace8f1d2csm24669967b3.42.2024.11.12.02.50.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Nov 2024 02:50:41 -0800 (PST) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-6e5b7cd1ef5so46627907b3.1; Tue, 12 Nov 2024 02:50:41 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCVmlb142wAwJbk5buebo9G5A6vscfVNpFYfhZeclzN3M6xMAklg+zhTxOaxFjUlSpQkB813F2YTwwlo@vger.kernel.org, AJvYcCWmdmIU5WuaVRMxI/D0g2jZA5iurLSA6D0mHYXDhmHRhRDVP1Ey/pYVaFh62vh7KnBQBkHzvDXhClUL7ZqjdpXfQqE=@vger.kernel.org, AJvYcCX0xIWwHJ7WRgPt2HrdmBQjnuVPwJeyL8G0PjooOCXvDxrmJN4r9nb7C+mwvVvFpbFGeQA44kax/++C5Om0@vger.kernel.org X-Received: by 2002:a05:690c:48c8:b0:6e3:2192:e0e6 with SMTP id 00721157ae682-6eaddda2d9fmr160448687b3.14.1731408641672; Tue, 12 Nov 2024 02:50:41 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20230209133507.150571-1-clement.leger@bootlin.com> <20230209133507.150571-3-clement.leger@bootlin.com> <20230215092933.2f71ece0@fixe.home> <20230215115441.361aed53@fixe.home> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 12 Nov 2024 11:50:29 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/2] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree To: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Thomas Petazzoni , Herve Codina , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Gareth Williams , Wolfram Sang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Cl=C3=A9ment, On Wed, Feb 15, 2023 at 12:31=E2=80=AFPM Geert Uytterhoeven wrote: > On Wed, Feb 15, 2023 at 11:52 AM Cl=C3=A9ment L=C3=A9ger > wrote: > > Le Wed, 15 Feb 2023 09:29:33 +0100, > > Cl=C3=A9ment L=C3=A9ger a =C3=A9crit : > > > Le Tue, 14 Feb 2023 17:25:14 +0100, > > > Geert Uytterhoeven a =C3=A9crit : > > > > On Thu, Feb 9, 2023 at 2:32 PM Cl=C3=A9ment L=C3=A9ger wrote: > > > > > The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. S= ince this > > > > > configuration targets only the RZ/N1D, it is named r9a06g032-rzn1= d400-eb. > > > > > It adds support for the 2 additional switch ports (port C and D) = that are > > > > > available on that board. > > > > > > > > > > Signed-off-by: Cl=C3=A9ment L=C3=A9ger > > > > > > > > Thanks for your patch! > > > > > > > > > --- /dev/null > > > > > +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-eb.dts > > > > > > + pinctrl-0 =3D <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <= &pins_eth4>, > > > > > + <&pins_mdio1>; > > > > > + > > > > > + mdio { > > > > > + /* CN15 and CN16 switches must be configured in M= DIO2 mode */ > > > > > + switch0phy1: ethernet-phy@1 { > > > > > + reg =3D <1>; > > > > > + marvell,reg-init =3D <3 16 0 0x1010>; > > > > > > > > marvell,reg-init is not documented in any DT bindings document? > > > > > > Indeed, this is not somethiong that should be made available here. It= 's > > > only inverting the LED polarity but supported by some internal patch. > > > I'll remove that. > > > I actually was confused by a property I added in another device-tree bu= t > > marvell,reg-init exists, is handled by the marvell phy driver and used > > in a few device-trees. Strangely, it is not documented anywhere. So I > > can either remove that (and the LED won't work properly) or let it live > > depending on what you prefer. > > In that case, please keep it. > But the property really should be documented, one day... Any plans to follow-up? Thanks! Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds