* [PATCH v2 0/2] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S
@ 2023-10-16 10:53 Claudiu
2023-10-16 10:53 ` [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-10-16 10:53 ` [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
0 siblings, 2 replies; 5+ messages in thread
From: Claudiu @ 2023-10-16 10:53 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-renesas-soc, devicetree, linux-kernel, claudiu.beznea,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
This series enables Renesas RZ/G3S (R9A08G045) SDHI1 and SDHI2.
SDHI1 is connected to a uSD interface available on Smarc-II carrier
board while SDHI2 is connected to a uSD interface available on
RZ/G3S Smarc Module (SoM).
Thank you,
Claudiu Beznea
[1] https://lore.kernel.org/all/20231006103959.197485-1-claudiu.beznea.uj@bp.renesas.com/
Changes in v2:
- addressed review comments
- remove patches from series that were already integrated
Claudiu Beznea (2):
arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
arm64: dts: renesas: rzg3s-smarc: Enable SDHI1
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 49 ++++++++++++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 65 +++++++++++++++++++
2 files changed, 114 insertions(+)
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
2023-10-16 10:53 [PATCH v2 0/2] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
@ 2023-10-16 10:53 ` Claudiu
2023-11-17 8:48 ` Geert Uytterhoeven
2023-10-16 10:53 ` [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
1 sibling, 1 reply; 5+ messages in thread
From: Claudiu @ 2023-10-16 10:53 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-renesas-soc, devicetree, linux-kernel, claudiu.beznea,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI0,
IRQ0, IRQ1. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0, IRQ1 is done
with a switch button. To be able to select b/w these a compilation flag has
been added (SW_SD2_EN) at the moment being instantiated to select SDHI2.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v2:
- remove pinctrl-1 and vqmmc regulator as UHS is not supported by SDHI2
- fixed typos in commit message and code
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index a199de8f8b02..01a4a9da7afc 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -13,14 +13,21 @@
* @SW_SD0_DEV_SEL:
* 0 - SD0 is connected to eMMC
* 1 - SD0 is connected to uSD0 card
+ * @SW_SD2_EN:
+ * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
+ * 1 - SD2 is connected to SoC
*/
#define SW_SD0_DEV_SEL 1
+#define SW_SD2_EN 1
/ {
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
aliases {
mmc0 = &sdhi0;
+#if SW_SD2_EN
+ mmc2 = &sdhi2;
+#endif
};
chosen {
@@ -63,6 +70,15 @@ reg_1p8v: regulator1 {
regulator-always-on;
};
#endif
+
+ vcc_sdhi2: regulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&extal_clk {
@@ -100,6 +116,17 @@ &sdhi0 {
};
#endif
+#if SW_SD2_EN
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_sdhi2>;
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ status = "okay";
+};
+#endif
+
&pinctrl {
sdhi0_pins: sd0 {
data {
@@ -139,4 +166,26 @@ sdhi0_emmc_pins: sd0-emmc {
"SD0_CLK", "SD0_CMD", "SD0_RST#";
power-source = <1800>;
};
+
+ sdhi2_pins: sd2 {
+ data {
+ pins = "P11_2", "P11_3", "P12_0", "P12_1";
+ input-enable;
+ };
+
+ ctrl {
+ pins = "P11_1";
+ input-enable;
+ };
+
+ mux {
+ pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
+ <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
+ <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
+ <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
+ <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
+ <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
+ <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
+ };
+ };
};
--
2.39.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1
2023-10-16 10:53 [PATCH v2 0/2] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-16 10:53 ` [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
@ 2023-10-16 10:53 ` Claudiu
2023-11-17 8:50 ` Geert Uytterhoeven
1 sibling, 1 reply; 5+ messages in thread
From: Claudiu @ 2023-10-16 10:53 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt,
conor+dt
Cc: linux-renesas-soc, devicetree, linux-kernel, claudiu.beznea,
Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add SDHI1 to RZ/G3S Smarc Carrier-II board. This is connected to a uSD
interface. Although Vccq doesn't cross the boundary of SoM it has
been added to RZ/G3S Smarc Carrier-II dtsi to have all the bits related to
SDHI1 in a single place. At the moment SoM is used only with RZ/G3S Smarc
Carrier-II board.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v2:
- change regulators' names to regulator-vcc-sdhi1 and
regulator-vccq-sdhi1
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 65 ++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
index e7073a09ed2e..214520137230 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
@@ -11,6 +11,26 @@
/ {
aliases {
serial0 = &scif0;
+ mmc1 = &sdhi1;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
};
};
@@ -19,6 +39,38 @@ scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};
+
+ sdhi1_pins: sd1 {
+ data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <3300>;
+ };
+
+ ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ cd {
+ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
+ };
+ };
+
+ sdhi1_pins_uhs: sd1-uhs {
+ data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <1800>;
+ };
+
+ ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <1800>;
+ };
+
+ cd {
+ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
+ };
+ };
};
&scif0 {
@@ -26,3 +78,16 @@ &scif0 {
pinctrl-0 = <&scif0_pins>;
status = "okay";
};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <125000000>;
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2
2023-10-16 10:53 ` [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
@ 2023-11-17 8:48 ` Geert Uytterhoeven
0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2023-11-17 8:48 UTC (permalink / raw)
To: Claudiu
Cc: magnus.damm, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-renesas-soc, devicetree, linux-kernel, Claudiu Beznea
Hi Claudiu,
Thanks for the update!
On Mon, Oct 16, 2023 at 12:54 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI0,
> IRQ0, IRQ1. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0, IRQ1 is done
SSI0
> with a switch button. To be able to select b/w these a compilation flag has
> been added (SW_SD2_EN) at the moment being instantiated to select SDHI2.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.8, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1
2023-10-16 10:53 ` [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Claudiu
@ 2023-11-17 8:50 ` Geert Uytterhoeven
0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2023-11-17 8:50 UTC (permalink / raw)
To: Claudiu
Cc: magnus.damm, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-renesas-soc, devicetree, linux-kernel, Claudiu Beznea
On Mon, Oct 16, 2023 at 12:54 PM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add SDHI1 to RZ/G3S Smarc Carrier-II board. This is connected to a uSD
> interface. Although Vccq doesn't cross the boundary of SoM it has
> been added to RZ/G3S Smarc Carrier-II dtsi to have all the bits related to
> SDHI1 in a single place. At the moment SoM is used only with RZ/G3S Smarc
> Carrier-II board.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>
> Changes in v2:
> - change regulators' names to regulator-vcc-sdhi1 and
> regulator-vccq-sdhi1
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.8.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
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2023-10-16 10:53 [PATCH v2 0/2] arm64: dts: renesas: Add SDHI1 and SDHI2 for RZ/G3S Claudiu
2023-10-16 10:53 ` [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Claudiu
2023-11-17 8:48 ` Geert Uytterhoeven
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