From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org,
conor+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, p.zabel@pengutronix.de,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH v5 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver
Date: Thu, 23 Oct 2025 10:00:21 +0200 [thread overview]
Message-ID: <CAMuHMdXF14x68Wk5YdOBS2D2N6LtnQjfGzrsMdSJegX-gc3faQ@mail.gmail.com> (raw)
In-Reply-To: <20251007133657.390523-3-claudiu.beznea.uj@bp.renesas.com>
Hi Claudiu,
On Tue, 7 Oct 2025 at 15:37, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
> only as a root complex, with a single-lane (x1) configuration. The
> controller includes Type 1 configuration registers, as well as IP
> specific registers (called AXI registers) required for various adjustments.
>
> Hardware manual can be downloaded from the address in the "Link" section.
> The following steps should be followed to access the manual:
> 1/ Click the "User Manual" button
> 2/ Click "Confirm"; this will start downloading an archive
> 3/ Open the downloaded archive
> 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables
> 5/ Open the file r01uh1014ej*-rzg3s.pdf
>
> Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> +static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data,
> + struct msi_msg *msg)
> +{
> + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data);
> + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
> + u32 drop_mask = RZG3S_PCI_MSIRCVWADRL_ENA |
> + RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA;
This should include bit 2 (which is hardwired to zero (for now)),
so I think you better add
#define RZG3S_PCI_MSIRCVWADRL_ADDR GENMASK(31, 3)
> + u32 lo, hi;
> +
> + /*
> + * Enable and msg data enable bits are part of the address lo. Drop
> + * them.
> + */
> + lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & ~drop_mask;
... and use FIELD_GET() with the new definition here.
> + hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU);
> +
> + msg->address_lo = lo;
> + msg->address_hi = hi;
> + msg->data = data->hwirq;
> +}
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2025-10-23 8:05 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 13:36 [PATCH v5 0/6] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-10-07 13:36 ` [PATCH v5 1/6] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Claudiu
2025-10-10 14:29 ` Rob Herring
2025-10-10 14:32 ` Rob Herring
2025-10-07 13:36 ` [PATCH v5 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver Claudiu
2025-10-19 6:52 ` Manivannan Sadhasivam
2025-10-22 19:49 ` Bjorn Helgaas
2025-10-23 5:11 ` Claudiu Beznea
2025-10-23 15:55 ` Bjorn Helgaas
2025-10-24 6:18 ` Claudiu Beznea
2025-10-23 7:55 ` Geert Uytterhoeven
2025-10-23 8:00 ` Geert Uytterhoeven [this message]
2025-10-23 9:34 ` Claudiu Beznea
2025-10-23 11:02 ` Geert Uytterhoeven
2025-10-23 11:23 ` Claudiu Beznea
2025-10-23 14:21 ` Geert Uytterhoeven
2025-10-07 13:36 ` [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node Claudiu
2025-10-07 13:44 ` Biju Das
2025-10-10 11:17 ` Claudiu Beznea
2025-10-10 11:36 ` Biju Das
2025-10-11 1:39 ` Biju Das
2025-10-19 6:57 ` Manivannan Sadhasivam
2025-10-20 6:15 ` Claudiu Beznea
2025-10-21 2:16 ` Manivannan Sadhasivam
2025-10-07 13:36 ` [PATCH v5 4/6] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Claudiu
2025-10-08 12:15 ` Geert Uytterhoeven
2025-10-07 13:36 ` [PATCH v5 5/6] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-10-07 13:36 ` [PATCH v5 6/6] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
2025-10-08 12:12 ` Geert Uytterhoeven
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