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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id 3f1490d57ef6-e0353d591d8sm261816276.12.2024.06.28.02.13.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jun 2024 02:13:54 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-64a6bf15db9so3481427b3.0; Fri, 28 Jun 2024 02:13:54 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCU/OjhH6AcRp7qTcIaNDiKSAYERaL03mUndBc+bKSD48eOUJLfo0d3MBXIRJfS9rlWKP33Qihs3N2I26aVDJAYJNfzguj2HjHH5vWfxGT3qdsxTSJK1hL18nuwf16XgynH5k5Rrk1o9hz2PLMbWEHM7GdWXQM78ayvv/ZSbzoeKDax1I7QSHllfPcc0AY6Z6zQzWN0Sv6bvoZpi/x1zYCx7MBhRHAPQWomdjrC6yTiBBrh8gsuJwf4Z2wYIaq7gu9M+ X-Received: by 2002:a05:690c:3709:b0:64b:44f2:70fb with SMTP id 00721157ae682-64b44f272f0mr5563117b3.41.1719566033879; Fri, 28 Jun 2024 02:13:53 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240625121358.590547-1-claudiu.beznea.uj@bp.renesas.com> <20240625121358.590547-8-claudiu.beznea.uj@bp.renesas.com> <6289f329-118f-4970-a525-75c3a48bd28b@tuxon.dev> <2f162986-33c5-4d80-958c-4f857adaad20@tuxon.dev> <79c26030-4b92-4ef3-b8ce-d011f492161b@tuxon.dev> In-Reply-To: <79c26030-4b92-4ef3-b8ce-d011f492161b@tuxon.dev> From: Geert Uytterhoeven Date: Fri, 28 Jun 2024 11:13:42 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to describe the register offsets To: claudiu beznea Cc: Biju Das , Chris Brandt , "andi.shyti@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "geert+renesas@glider.be" , "magnus.damm@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "p.zabel@pengutronix.de" , "wsa+renesas@sang-engineering.com" , "linux-renesas-soc@vger.kernel.org" , "linux-i2c@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Claudiu, On Fri, Jun 28, 2024 at 10:12=E2=80=AFAM claudiu beznea wrote: > On 28.06.2024 11:09, Biju Das wrote: > >> -----Original Message----- > >> From: claudiu beznea > >> Sent: Friday, June 28, 2024 9:03 AM > >> Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to d= escribe the register offsets > >> > >> > >> > >> On 28.06.2024 10:55, Biju Das wrote: > >>> Hi Claudiu, > >>> > >>>> -----Original Message----- > >>>> From: claudiu beznea > >>>> Sent: Friday, June 28, 2024 8:32 AM > >>>> Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to > >>>> describe the register offsets > >>>> > >>>> Hi, Biju, > >>>> > >>>> On 28.06.2024 08:59, Biju Das wrote: > >>>>> Hi Claudiu, > >>>>> > >>>>>> -----Original Message----- > >>>>>> From: Claudiu > >>>>>> Sent: Tuesday, June 25, 2024 1:14 PM > >>>>>> Subject: [PATCH v2 07/12] i2c: riic: Define individual arrays to > >>>>>> describe the register offsets > >>>>>> > >>>>>> From: Claudiu Beznea > >>>>>> > >>>>>> Define individual arrays to describe the register offsets. In this > >>>>>> way we can describe different IP variants that share the same > >>>>>> register offsets but have differences in other characteristics. > >>>>>> Commit prepares for the addition > >>>> of fast mode plus. > >>>>>> > >>>>>> Signed-off-by: Claudiu Beznea > >>>>>> --- > >>>>>> > >>>>>> Changes in v2: > >>>>>> - none > >>>>>> > >>>>>> drivers/i2c/busses/i2c-riic.c | 58 > >>>>>> +++++++++++++++++++---------------- > >>>>>> 1 file changed, 31 insertions(+), 27 deletions(-) > >>>>>> > >>>>>> diff --git a/drivers/i2c/busses/i2c-riic.c > >>>>>> b/drivers/i2c/busses/i2c-riic.c index > >>>>>> 9fe007609076..8ffbead95492 100644 > >>>>>> --- a/drivers/i2c/busses/i2c-riic.c > >>>>>> +++ b/drivers/i2c/busses/i2c-riic.c > >>>>>> @@ -91,7 +91,7 @@ enum riic_reg_list { }; > >>>>>> > >>>>>> struct riic_of_data { > >>>>>> - u8 regs[RIIC_REG_END]; > >>>>>> + const u8 *regs; > >>>>> > >>>>> > >>>>> Since you are touching this part, can we drop struct and Use u8* as > >>>>> device_data instead? > >>>> > >>>> Patch 09/12 "i2c: riic: Add support for fast mode plus" adds a new m= ember to struct > >> riic_of_data. > >>>> That new member is needed to differentiate b/w hardware versions > >>>> supporting fast mode plus based on compatible. > >>> > >>> Are we sure RZ/A does not support fast mode plus? > >> > >> From commit description of patch 09/12: > >> > >> Fast mode plus is available on most of the IP variants that RIIC drive= r is working with. The > >> exception is (according to HW manuals of the SoCs where this IP is ava= ilable) the Renesas RZ/A1H. > >> For this, patch introduces the struct riic_of_data::fast_mode_plus. > >> > >> I checked the manuals of all the SoCs where this driver is used. > >> > >> I haven't checked the H/W manual? > >> > >> On the manual I've downloaded from Renesas web site the FMPE bit of RI= ICnFER is not available on > >> RZ/A1H. > > > > I just found RZ/A2M manual, it supports FMP and register layout looks s= imilar to RZ/G2L. > > I introduced struct riic_of_data::fast_mode_plus because of RZ/A1H. Do you need to check for that? The ICFER_FMPE bit won't be set unless the user specifies the FM+ clock-frequency. Setting clock-frequency beyond Fast Mode on RZ/A1H would be very wrong. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds