[PATCH v4 0/2] clk: renesas: r9a06g032: Add clock domain support

[PATCH v4 0/2] clk: renesas: r9a06g032: Add clock domain support

[Gareth Williams]

There are several clocks on the r9a06g032 which are currently not enabled
in their drivers that can be delegated to clock domain system for power
management. Therefore add support for clock domain functionality to the
r9a06g032 clock driver after updating the relevant dt-bindings file.

v4:
 - Removed unneeded initialisation of "error" in 
   create_add_module_clock.
 - Moved declaration of "index" to the start of r9a06g032_attach_dev.
 - Moved of_node_put(clkspec.np) call to after create_add_module_clock
   call in r9a06g032_attach_dev.
 - Added missing HCLK to UART0 example to show the clock added
   to the driver.
v3:
 - "managed" flag integrated into existing bit field.
 - Removed unneeded initialisation inside D_MODULE.
 - Removed the use of unneeded r9a06g032_clk_domain variable.
 - Removed error message prints that cannot occur.
 - Removed __init and __initconst from attach function and
   r9a06g032_clocks[].
 - Reordered r9a06g032_add_clk_domain call to after 
   devm_add_action_or_reset during probe.
 - Added clock type check when retrieving clocks from device tree.
 - Reordered of_node_put call to before error check in
   create_add_module_clock.
 - changed r9a06g032_detach_dev to a static function.
 - Added new #power-domain-cells property to the required properties.
 - Added "#power-domain-cells" and "power-domains" lines to examples.
v2:
 - Rebased onto kernel/git/geert/renesas-drivers.git

Gareth Williams (2):
  dt-bindings: clock: renesas,r9a06g032-sysctrl: Document power Domains
  clk: renesas: r9a06g032: Add clock domain support

 .../bindings/clock/renesas,r9a06g032-sysctrl.txt   |   7 +-
 drivers/clk/renesas/r9a06g032-clocks.c             | 230 ++++++++++++++-------
 2 files changed, 166 insertions(+), 71 deletions(-)

-- 
2.7.4

[PATCH v4 1/2] dt-bindings: clock: renesas,r9a06g032-sysctrl: Document power Domains

[Gareth Williams]

The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.

Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
 - Added missing HCLK to UART0 example to show the clock added
   to the driver.
 - Added Geert's Reviewed-by line.
v3:
 - Added new #power-domain-cells property to the required properties.
 - Added "#power-domain-cells" and "power-domains" lines to examples.
v2:
 - No changes.
---
 .../devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt        | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
index d60b997..30adb4c 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
 	- external (optional) RGMII_REFCLK
   - clock-names: Must be:
         clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+  - #power-domain-cells : Must be 0
 
 Examples
 --------
@@ -27,6 +28,7 @@ Examples
 		clocks = <&ext_mclk>, <&ext_rtc_clk>,
 				<&ext_jtag_clk>, <&ext_rgmii_ref>;
 		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+		#power-domain-cells = <0>;
 	};
 
   - Other nodes can use the clocks provided by SYSCTRL as in:
@@ -38,6 +40,7 @@ Examples
 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
-		clocks = <&sysctrl R9A06G032_CLK_UART0>;
-		clock-names = "baudclk";
+		clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		power-domains = <&sysctrl>;
 	};
-- 
2.7.4

Re: [PATCH v4 1/2] dt-bindings: clock: renesas,r9a06g032-sysctrl: Document power Domains

[Geert Uytterhoeven]

On Tue, May 28, 2019 at 1:55 PM Gareth Williams
<gareth.williams.jx@renesas.com> wrote:
> The driver is gaining power domain support, so add the new property
> to the DT binding and update the examples.
>
> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v4:
>  - Added missing HCLK to UART0 example to show the clock added
>    to the driver.
>  - Added Geert's Reviewed-by line.

Thanks for the update, will queue in clock-renesas-for-v5.3.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds