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[209.85.128.180]) by smtp.gmail.com with ESMTPSA id 00721157ae682-63118e99dd5sm16527117b3.69.2024.06.18.00.56.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Jun 2024 00:56:19 -0700 (PDT) Received: by mail-yw1-f180.google.com with SMTP id 00721157ae682-630640c1e14so61855627b3.1; Tue, 18 Jun 2024 00:56:19 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUJDYNazC5t/By0MP6lZk+8Wbx+b+HkoVxnqFY8PZ+K97dMukhCxBsLhODbOgNpr8pPhgU4/QeoCkjxf9NSNEJQbID0YtxsBpBSybEnqqIL22MOy+6lPJosyEQ0lxg889p09MbRaBg2wBX8L44VY8lk9FZUMJAY01dNrCDL+UG3z7wvJUdg8Vcltd+MFWbqe6cKm70Y61Q6omWgvFZuTL06dYjUl6i9Uh2C0D56uX+66vgTA0uBePogHqcIBgGhZZ23 X-Received: by 2002:a05:690c:6a12:b0:620:31ca:599d with SMTP id 00721157ae682-63222d4b77dmr134135247b3.29.1718697379204; Tue, 18 Jun 2024 00:56:19 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240614071932.1014067-1-claudiu.beznea.uj@bp.renesas.com> <20240614071932.1014067-3-claudiu.beznea.uj@bp.renesas.com> <20240615-angler-occupier-6188a3187655@spud> <3d9ed0ec-ca9a-45b4-a633-8f7051d13cff@tuxon.dev> <20240617-subsoil-creed-04bf5f13d081@spud> <0a4ba0e5-3fb1-4ffc-b2d8-a4eb418707eb@tuxon.dev> In-Reply-To: <0a4ba0e5-3fb1-4ffc-b2d8-a4eb418707eb@tuxon.dev> From: Geert Uytterhoeven Date: Tue, 18 Jun 2024 09:56:07 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver To: claudiu beznea Cc: Conor Dooley , mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lee@kernel.org, alexandre.belloni@bootlin.com, magnus.damm@gmail.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Claudiu, On Tue, Jun 18, 2024 at 9:34=E2=80=AFAM claudiu beznea wrote: > On 17.06.2024 18:19, Conor Dooley wrote: > > On Mon, Jun 17, 2024 at 10:02:47AM +0300, claudiu beznea wrote: > >> On 15.06.2024 15:17, Conor Dooley wrote: > >>> On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote: > >>>> From: Claudiu Beznea > >>>> > >>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feed= s > >>>> the RTC and the tamper detector. Add documentation for the VBATTB cl= ock > >>>> driver. > >>>> > >>>> Signed-off-by: Claudiu Beznea > >>>> --- > >>>> .../clock/renesas,rzg3s-vbattb-clk.yaml | 90 ++++++++++++++++= +++ > >>>> 1 file changed, 90 insertions(+) > >>>> create mode 100644 Documentation/devicetree/bindings/clock/renesas,= rzg3s-vbattb-clk.yaml > >>>> > >>>> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-v= battb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbat= tb-clk.yaml > >>>> new file mode 100644 > >>>> index 000000000000..ef52a0c0f874 > >>>> --- /dev/null > >>>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-c= lk.yaml > >>>> + renesas,vbattb-osc-bypass: > >>>> + description: set when external clock is connected to RTXOUT pin FTR, this contradicts the explanation below, which states the external clock oscillator is connected to RTXIN. > >>>> + type: boolean > >>> > >>> When you say "external clock", is that an input or an output? > >> > >> I took that statement from the HW manual. As of the HW manual [1], tab= le > >> 42.2, that would be an input. > > > > Forgive me for not wanting to open the zip etc and find the information > > in the document, but why do you need an extra property? Is it not > > something you can determine from the clocks/clock-names properties? > > It can't be determined from clocks/clock-names as of my understanding. It > depends on the type of the input clock (crystal oscillator or external > hardware device generating the clock). > > > It sounds like an additional clock from your description, is it actuall= y > > different way to provide the second clock you mention above? > > This is the block diagram (see [1], only picture this time) of the module > controlling the clock. Please open it, it helps in understanding what I'l= l > explain above. > > The VBATTB blocks controlling the VBATTBCLK are: > - 32KHz-clock oscillator > - the mux controlled by BKSCCR.SOSEL > - the gate who's input is the mux output and XOSCCR.OUTEN > > To the 32 KHz-clock oscillator block could be connected: > 1/ either a crystal oscillator in which case it will be connected to both > RTXIN and RTXOUT pins (the direction of RTXOUT is wrong in this picture f= or > this case) > 2/ or a device (like [2]) generating a clock which has a single output an= d, > from my understanding and experience with devices like this, only RTXIN i= s > needed, RTXOUT is connected to the ground; for this case the 32KHz-clock > oscillator block from [1] need to be bypassed in which case the newly > introduced property will be used; this will select the XBYP on the mux. Sounds similar to the RAA215300 PMIC, which includes an ISL1208-derived RTC, where this was handled using two different clock names: https://elixir.bootlin.com/linux/v6.10-rc1/source/Documentation/devicetree/= bindings/regulator/renesas,raa215300.yaml#L49 https://elixir.bootlin.com/linux/v6.10-rc1/source/drivers/rtc/rtc-isl1208.c= #L869 Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds