Re: [PATCH v1 2/3] dt-bindings: riscv: convert plic bindings to json-schema

[Geert Uytterhoeven <geert@linux-m68k.org>]

Hi Sagar, Rob,

(replying to an old email, as this one seems to be the most appropriate)

On Tue, Sep 22, 2020 at 10:34 PM Rob Herring <robh@kernel.org> wrote:
> On Thu, Sep 10, 2020 at 04:14:03PM +0530, Sagar Kadam wrote:
> > Convert device tree bindings for SiFive's PLIC to YAML format
> >
> > Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com>

> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

> > +
> > +  '#address-cells':
> > +    const: 0
> > +    description: Should be <0> or more.
>
> Drop. 'or more' is wrong. If there's a case with more, it will need to
> be documented.

Why do we have the "'#address-cells': const: 0" at all...

> > +required:
> > +  - compatible
> > +  - '#address-cells'

... and why is it required?

> > +  - '#interrupt-cells'
> > +  - interrupt-controller
> > +  - reg
> > +  - interrupts-extended
> > +  - riscv,ndev
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    plic: interrupt-controller@c000000 {
> > +      #address-cells = <0>;
> > +      #interrupt-cells = <1>;
> > +      compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
> > +      interrupt-controller;
> > +      interrupts-extended = <
> > +        &cpu0_intc 11
> > +        &cpu1_intc 11 &cpu1_intc 9
> > +        &cpu2_intc 11 &cpu2_intc 9
> > +        &cpu3_intc 11 &cpu3_intc 9
> > +        &cpu4_intc 11 &cpu4_intc 9>;
> > +      reg = <0xc000000 0x4000000>;
> > +      riscv,ndev = <10>;
> > +    };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds