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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
	Simon Horman <horms@verge.net.au>,
	Magnus Damm <magnus.damm@gmail.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-sh@vger.kernel.org" <linux-sh@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v4 1/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
Date: Wed, 5 Aug 2015 12:44:10 +0200	[thread overview]
Message-ID: <CAMuHMdXdEV+41mH338bDbazzqOErDLQkBUAj2+uVX4Wupn1ABQ@mail.gmail.com> (raw)
In-Reply-To: <55C1D894.8070302@arm.com>

Hi Sudeep,

On Wed, Aug 5, 2015 at 11:34 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> On 05/08/15 09:58, Geert Uytterhoeven wrote:
>> Add the missing L2 cache-controller node. This will allow migration to
>> the generic l2c OF initialization.
>>
>> The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
>> 8 ways).
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

>> diff --git a/arch/arm/boot/dts/r8a7740.dtsi
>> b/arch/arm/boot/dts/r8a7740.dtsi
>> index d84714468cce18df..ddef5b1c68fa06b3 100644
>> --- a/arch/arm/boot/dts/r8a7740.dtsi
>> +++ b/arch/arm/boot/dts/r8a7740.dtsi
>> @@ -37,6 +37,22 @@
>>                       <0xc2000000 0x1000>;
>>         };
>>
>> +       L2: cache-controller {
>> +               compatible = "arm,pl310-cache";
>> +               reg = <0xf0100000 0x1000>;
>> +               interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
>> +               power-domains = <&pd_a3sm>;
>> +               arm,data-latency = <3 3 3>;
>> +               arm,tag-latency = <2 2 2>;
>> +               arm,shared-override;
>> +               cache-unified;
>> +               cache-level = <2>;
>> +               cache-size = <0x40000>;
>> +               cache-sets = <1024>;
>> +               cache-block-size = <32>;
>> +               cache-line-size = <32>;
>
>
> Any particular reason whey you need all this cache-* properties ? Is

To describe the cache as good as possible.

> something broken on these SoCs ? We should be able to get most of these
> information from the SoC(reading some registers). It's good to avoid
> passing them via DT if they can be discovered from hardware.

So we have all these documented properties in
Documentation/devicetree/bindings/arm/l2cc.txt, but they're not meant to
be used?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2015-08-05 10:44 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-05  8:58 [PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling Geert Uytterhoeven
     [not found] ` <1438765090-823-1-git-send-email-geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
2015-08-05  8:58   ` [PATCH v4 1/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-08-05  9:34     ` Sudeep Holla
2015-08-05 10:44       ` Geert Uytterhoeven [this message]
     [not found]         ` <CAMuHMdXdEV+41mH338bDbazzqOErDLQkBUAj2+uVX4Wupn1ABQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-08-05 10:58           ` Sudeep Holla
     [not found]             ` <55C1EC3C.9000407-5wv7dgnIgG8@public.gmane.org>
2015-08-06 16:21               ` Geert Uytterhoeven
2015-08-07  9:45                 ` Sudeep Holla
2015-11-20 16:14                   ` Geert Uytterhoeven
2015-11-26 11:59                     ` Sudeep Holla
2015-08-05  8:58   ` [PATCH v4 2/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node Geert Uytterhoeven
2015-08-05  8:58   ` [PATCH v4 3/6] ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-08-05  8:58   ` [PATCH v4 6/6] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers Geert Uytterhoeven
2015-08-05  8:58 ` [PATCH v4 4/6] ARM: shmobile: sh73a0 dtsi: Add L1 cache information to CPU nodes Geert Uytterhoeven
2015-08-05  8:58 ` [PATCH v4 5/6] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization Geert Uytterhoeven
2015-08-06  0:35 ` [PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling Simon Horman
2015-08-06  7:17   ` Geert Uytterhoeven
2015-08-07  0:34     ` Simon Horman

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