From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Paul Barker <paul.barker.ct@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/9] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
Date: Mon, 17 Jun 2024 14:02:17 +0200 [thread overview]
Message-ID: <CAMuHMdXe8aaweQJ2=V7ksKTqcJCnqewKhSrrO4h7X924Vbk-_Q@mail.gmail.com> (raw)
In-Reply-To: <20240611113204.3004-3-paul.barker.ct@bp.renesas.com>
Hi Paul,
On Tue, Jun 11, 2024 at 1:33 PM Paul Barker
<paul.barker.ct@bp.renesas.com> wrote:
> The variable naming in the various OEN functions has been confusing. We
> were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get()
> and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the
> read_oen() and write_oen() functions. This doesn't make sense, the first
> of these isn't actually an offset and the second is not needed for
> RZ/V2H but leads to confusion with the bit variable used within these
> functions.
>
> To tidy this up, instead pass the _pin variable directly to the
> read_oen() and write_oen() functions with consistent naming. Then
> rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port
> and pin numbers it needs.
>
> Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give
> a single translation function which returns an error if the pin doesn't
> support OEN. While we're here, remove an unnecessary branch and clarify
> the variable naming.
>
> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> ---
> Changes v1->v2:
> * Merged patches 1 & 2 from the previous series, updated to be
> compatible with recent patches adding RZ/V2H support.
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -994,53 +994,43 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
> return false;
> }
>
> -static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
> +static int rzg3s_pin_to_oen_bit(const struct rzg2l_hwcfg *hwcfg, u32 caps, u32 port, u8 pin)
> {
> - if (!(caps & PIN_CFG_OEN))
> - return false;
> + u8 bit = pin * 2;
>
> - if (pin > max_pin)
> - return false;
> + if (!(caps & PIN_CFG_OEN) || pin > hwcfg->oen_max_pin)
> + return -EINVAL;
>
> - return true;
> + if (port == hwcfg->oen_max_port)
> + bit += 1;
> +
> + return bit;
> }
>
> -static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
> +static u32 rzg3s_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, unsigned int _pin)
> {
> - if (pin)
> - pin *= 2;
> + u32 port = RZG2L_PIN_ID_TO_PORT(_pin);
> + u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
It's OK to use RZG2L_PIN_ID_TO_PIN() unconditionally, as RZ/G3S does
not have any dedicated pins with the OEN capability, right?
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2024-06-17 12:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-11 11:31 [PATCH v2 0/9] Configure GbEth for RGMII on RZ/G2L family Paul Barker
2024-06-11 11:31 ` [PATCH v2 1/9] pinctrl: renesas: rzg2l: Clarify OEN read/write support Paul Barker
2024-06-17 11:52 ` Geert Uytterhoeven
2024-06-17 14:22 ` Paul Barker
2024-06-11 11:31 ` [PATCH v2 2/9] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions Paul Barker
2024-06-17 12:02 ` Geert Uytterhoeven [this message]
2024-06-25 19:56 ` Paul Barker
2024-06-26 6:19 ` claudiu beznea
2024-06-11 11:31 ` [PATCH v2 3/9] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Paul Barker
2024-06-17 12:15 ` Geert Uytterhoeven
2024-06-11 11:31 ` [PATCH v2 4/9] arm64: dts: renesas: rzg2l: Enable Ethernet TXC output Paul Barker
2024-06-11 11:31 ` [PATCH v2 5/9] arm64: dts: renesas: rzg2lc: " Paul Barker
2024-06-11 11:32 ` [PATCH v2 6/9] arm64: dts: renesas: rzg2ul: " Paul Barker
2024-06-11 11:32 ` [PATCH v2 7/9] arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8V Paul Barker
2024-06-11 11:32 ` [PATCH v2 8/9] arm64: dts: renesas: rzg2lc: " Paul Barker
2024-06-11 11:32 ` [PATCH v2 9/9] arm64: dts: renesas: rzg2ul: " Paul Barker
2024-06-11 13:14 ` [PATCH v2 0/9] Configure GbEth for RGMII on RZ/G2L family Linus Walleij
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAMuHMdXe8aaweQJ2=V7ksKTqcJCnqewKhSrrO4h7X924Vbk-_Q@mail.gmail.com' \
--to=geert@linux-m68k.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=magnus.damm@gmail.com \
--cc=paul.barker.ct@bp.renesas.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).