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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id ch11-20020a05622a40cb00b0033b30e8e7a5sm2574690qtb.58.2022.08.19.01.25.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Aug 2022 01:25:25 -0700 (PDT) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-324ec5a9e97so103272687b3.7; Fri, 19 Aug 2022 01:25:24 -0700 (PDT) X-Received: by 2002:a5b:bcd:0:b0:68f:b4c0:7eca with SMTP id c13-20020a5b0bcd000000b0068fb4c07ecamr6672282ybr.202.1660897524733; Fri, 19 Aug 2022 01:25:24 -0700 (PDT) MIME-Version: 1.0 References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220815151451.23293-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <07342070-d96c-59fc-f9dd-b65cd742d97a@microchip.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 19 Aug 2022 10:25:11 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK To: "Lad, Prabhakar" Cc: Conor Dooley , "Lad, Prabhakar" , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , LKML , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Prabhakar, On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar wrote: > On Mon, Aug 15, 2022 at 8:00 PM wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > > Enable the minimal blocks required for booting the Renesas RZ/Five > > > SMARC EVK with initramfs. > > > > > > Signed-off-by: Lad Prabhakar > > > --- > > > v1->v2 > > > * New patch > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/renesas/Makefile | 2 ++ > > > .../boot/dts/renesas/r9a07g043f01-smarc.dts | 16 ++++++++++ > > > .../boot/dts/renesas/rzfive-smarc-som.dtsi | 22 +++++++++++++ > > > arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++ > > > 5 files changed, 73 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/renesas/Makefile > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts > > > create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > > > > Just to sort out some of my own confusion here - is the smarc EVK > > shared between your arm boards and the riscv ones? Or just the > > peripherals etc on the soc? > > > RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL > SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC > SoM and still be used. > > > If it is the forver, does the approach suggested here for the > > allwinner stuff make sense to also use for risc-v stuff with > > shared parts of devicetrees? > > https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/ > > > it does make sense. But I wonder where we would place the common > shared dtsi that can be used by two arch's. You can keep it under arch/arm/boot/dts/renesas/, and refer to it from riscv as . Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and e.g. cros-ec-keyboard.dtsi. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds