From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Magnus Damm <magnus.damm@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 2/3] clk: renesas: Add family-specific clock driver for RZ/V2H(P)
Date: Fri, 12 Jul 2024 17:23:07 +0200 [thread overview]
Message-ID: <CAMuHMdXuyQZ=SFfQa5kvZTwYa0uRXc7khJ-vOYBRE5SCd11rPw@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8vABF6vg+J7DAGzgnw8612oe6VfJkc5y-krySvnpAnPkQ@mail.gmail.com>
Hi Prabhakar,
On Fri, Jul 12, 2024 at 5:14 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Fri, Jul 12, 2024 at 12:59 PM Geert Uytterhoeven
> > On Thu, Jun 27, 2024 at 6:14 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add family-specific clock driver for RZ/V2H(P) SoCs.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v2->v3
> > > - Dropped num_hw_resets from struct rzv2h_cpg_priv
> > > - Dropped range_check for module clocks
> > > - Made mon_index to s8 instead of u8 in struct rzv2h_mod_clk
> > > - Added support for critical module clocks with DEF_MOD_CRITICAL
> > > - Added check for mon_index in rzv2h_mod_clock_endisable and
> > > rzv2h_mod_clock_is_enabled()
> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.h
> > > +/**
> > > + * struct rzv2h_reset - Reset definitions
> > > + *
> > > + * @reset_index: reset register index
> > > + * @reset_bit: reset bit
> > > + * @mon_index: monitor register index
> > > + * @mon_bit: monitor bit
> > > + */
> > > +struct rzv2h_reset {
> > > + u8 reset_index;
> > > + u8 reset_bit;
> > > + u8 mon_index;
> > > + u8 mon_bit;
> > > +};
> > > +
> > > +#define RST_ID(x, y) ((((x) * 16)) + (y))
> > > +
> > > +#define DEF_RST_BASE(_id, _resindex, _resbit, _monindex, _monbit) \
> > > + [_id] = { \
> >
> > Indexing by _id means the reset array will be very sparse. E.g. the
> > innocent-looking r9a09g057_resets[] with only a single entry takes
> > 600 bytes.
> >
> > If you do need the full array for indexing, please allocate and
> > populate it at runtime.
> >
> OK, I will use the radix tree for resets (is that OK)?
You mean XArray? include/linux/radix-tree.h has:
/* Keep unconverted code working */
#define radix_tree_root xarray
#define radix_tree_node xa_node
Given a single xa_node is already 576 bytes, just allocating the full
linear reset array at runtime is probably better.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2024-07-12 15:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 16:13 [PATCH v3 0/3] Add CPG support for RZ/V2H(P) SoC Prabhakar
2024-06-27 16:13 ` [PATCH v3 1/3] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Prabhakar
2024-07-01 13:23 ` Krzysztof Kozlowski
2024-07-12 11:58 ` Geert Uytterhoeven
2024-07-12 13:47 ` Lad, Prabhakar
2024-06-27 16:13 ` [PATCH v3 2/3] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Prabhakar
2024-07-12 11:59 ` Geert Uytterhoeven
2024-07-12 15:13 ` Lad, Prabhakar
2024-07-12 15:23 ` Geert Uytterhoeven [this message]
2024-07-12 15:28 ` Lad, Prabhakar
2024-07-12 17:11 ` Geert Uytterhoeven
2024-07-15 8:43 ` Lad, Prabhakar
2024-07-15 9:41 ` Geert Uytterhoeven
2024-07-15 9:55 ` Lad, Prabhakar
2024-06-27 16:13 ` [PATCH v3 3/3] clk: renesas: Add RZ/V2H(P) CPG driver Prabhakar
2024-07-12 12:00 ` Geert Uytterhoeven
2024-07-12 15:14 ` Lad, Prabhakar
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