From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7FFAC6369E for ; Wed, 18 Nov 2020 15:24:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8480E206C0 for ; Wed, 18 Nov 2020 15:24:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uFCwaMaO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726484AbgKRPYa (ORCPT ); Wed, 18 Nov 2020 10:24:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726224AbgKRPY3 (ORCPT ); Wed, 18 Nov 2020 10:24:29 -0500 Received: from mail-qk1-x742.google.com (mail-qk1-x742.google.com [IPv6:2607:f8b0:4864:20::742]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38D92C0613D6 for ; Wed, 18 Nov 2020 07:24:29 -0800 (PST) Received: by mail-qk1-x742.google.com with SMTP id d9so2090013qke.8 for ; Wed, 18 Nov 2020 07:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Fle8ClFYzcj6GfpSzRipzzKtCibAbBbslIkjI+AUvgc=; b=uFCwaMaOuYdqw4Gmvzziuv+cKJXjaWg+O30XofsrjlUpVEpkZW6eXtVOYXJIynnQ1Q lH6wGhVB+H9ilEm/2BsZxlhmxx8JCk0wtEnlpa6sZanxnDYCh5sNCRaSR1m2JypbuFGO RwvuZpBx+ywJju9RId62y0nzsDyfYz3ojOGbVYBhYhDMsca49SzQsq6A9cC6E9+KC/v9 0Y9k2nBPY28I0+zCrZw6O5DGwkXQ+Cew5MwfiU0DqdgFd30bL3RX178qX3zurevOVVAY Qia6lv5MAF/o6fhmOA/Xw2zCiw39PzwOjNher+Z/286Agz7meYvrjvTulHbjzL7Pvry7 t0Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Fle8ClFYzcj6GfpSzRipzzKtCibAbBbslIkjI+AUvgc=; b=Ox37gUhRKYXxpWXw42ia7eE0eMz/k/fwYfwQF0cmPTgVfcVp/8Sjq/lF6NbxLARFeZ GoUD/NfncxyluNGkjptHy3UuY802/Ky3rL9xUg8i1irsfwaQnzPDIzIKNcIN7bOc9WhB POg+2PllwAkKSRova0MzmwK4yK2pqJPOGaJcGwnEf7TsKPEQW1D/ecpsJmVxZkjYX7y8 4V89UllnrgZqdcwgPGV505kw9oTAECyBuRDY8IfAWLG2pvl+noHet66aIjxq+5lCevdX fZ7xfKtDsQQdOtvsamNcDyohvc45jIu+akhLAeZ3aHy8ATf7AURcM7XI3O0ThKD6w9rh +QRg== X-Gm-Message-State: AOAM530uwiDqZ50XPWRMNjxNv2GYtfW4zv5l6UgKjbG+Q6AzO7F2prGr FPJwbhv5jetpaI11RPP75/Ba4BVHr/BxDfbM849VWg== X-Google-Smtp-Source: ABdhPJw8gl/nvg3ZUtxwIZOKLIFYuEwxoN044AJNe0ORQz0AOrqZagvnjB/wXJ8KYl560v6qKtiAftgU43W9Ttqb5W8= X-Received: by 2002:ae9:ed89:: with SMTP id c131mr5019963qkg.421.1605713068425; Wed, 18 Nov 2020 07:24:28 -0800 (PST) MIME-Version: 1.0 References: <20201114084613.13503-1-grzegorz.jaszczyk@linaro.org> <20201114084613.13503-6-grzegorz.jaszczyk@linaro.org> <0ae5656f-20d7-95dc-f88a-7125edfbfb75@ti.com> In-Reply-To: <0ae5656f-20d7-95dc-f88a-7125edfbfb75@ti.com> From: Grzegorz Jaszczyk Date: Wed, 18 Nov 2020 16:24:16 +0100 Message-ID: Subject: Re: [PATCH 5/6] remoteproc/pru: Add support for various PRU cores on K3 AM65x SoCs To: Suman Anna Cc: Ohad Ben Cohen , Bjorn Andersson , Mathieu Poirier , linux-remoteproc@vger.kernel.org, Rob Herring , Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "Bajjuri, Praneeth" , Roger Quadros Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Suman, On Tue, 17 Nov 2020 at 21:09, Suman Anna wrote: > > Hi Greg, > > On 11/14/20 2:46 AM, Grzegorz Jaszczyk wrote: > > From: Suman Anna > > > > The K3 AM65x family of SoCs have the next generation of the PRU-ICSS > > processor subsystem, commonly referred to as ICSSG. Each ICSSG processor > > subsystem on AM65x SR1.0 contains two primary PRU cores and two new > > auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised > > ICSSG IP that is based off the subsequent IP revision used on J721E > > SoCs. This IP instance has two new custom auxiliary PRU cores called > > Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. > > > > Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than > > a PRU), Control and debug feature sets, but is different in terms of > > sub-modules integrated around it and does not have the full capabilities > > associated with a PRU core. The RTU core is typically used to aid a > > PRU core in accelerating data transfers, while the Tx_PRU cores is > > normally used to control the TX L2 FIFO if enabled in Ethernet > > applications. Both can also be used to run independent applications. > > The RTU and Tx_PRU cores though share the same Data RAMs as the PRU > > cores, so the memories have to be partitioned carefully between different > > applications. The new cores also support a new sub-module called Task > > Manager to support two different context thread executions. > > > > Enhance the existing PRU remoteproc driver to support these new PRU, RTU > > and Tx PRU cores by using specific compatibles. The initial names for the > > firmware images for each PRU core are retrieved from DT nodes, and can > > be adjusted through sysfs if required. > > > > The PRU remoteproc driver has to be specifically modified to use a > > custom memcpy function within its ELF loader implementation for these > > new cores in order to overcome a limitation with copying data into each > > of the core's IRAM memories. These memory ports support only 4-byte > > writes, and any sub-word order byte writes clear out the remaining > > bytes other than the bytes being written within the containing word. > > The default ARM64 memcpy also cannot be used as it throws an exception > > when the preferred 8-byte copy operation is attempted. This choice is > > made by using a state flag that is set only on K3 SoCs. > > > > Signed-off-by: Suman Anna > > Co-developed-by: Grzegorz Jaszczyk > > Signed-off-by: Grzegorz Jaszczyk > > --- > > drivers/remoteproc/pru_rproc.c | 141 ++++++++++++++++++++++++++++++--- > > 1 file changed, 132 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c > > index 33806ddcbd5d..04c9f07799e2 100644 > > --- a/drivers/remoteproc/pru_rproc.c > > +++ b/drivers/remoteproc/pru_rproc.c > > @@ -46,9 +46,13 @@ > > #define PRU_DEBUG_GPREG(x) (0x0000 + (x) * 4) > > #define PRU_DEBUG_CT_REG(x) (0x0080 + (x) * 4) > > > > -/* PRU Core IRAM address masks */ > > +/* PRU/RTU/Tx_PRU Core IRAM address masks */ > > #define PRU0_IRAM_ADDR_MASK 0x34000 > > #define PRU1_IRAM_ADDR_MASK 0x38000 > > +#define RTU0_IRAM_ADDR_MASK 0x4000 > > +#define RTU1_IRAM_ADDR_MASK 0x6000 > > +#define TX_PRU0_IRAM_ADDR_MASK 0xa000 > > +#define TX_PRU1_IRAM_ADDR_MASK 0xc000 > > > > /* PRU device addresses for various type of PRU RAMs */ > > #define PRU_IRAM_DA 0 /* Instruction RAM */ > > @@ -73,12 +77,38 @@ enum pru_iomem { > > PRU_IOMEM_MAX, > > }; > > > > +/** > > + * enum pru_type - PRU core type identifier > > + * > > + * @PRU_TYPE_PRU: Programmable Real-time Unit > > + * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit > > + * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit > > + * @PRU_TYPE_MAX: just keep this one at the end > > + */ > > +enum pru_type { > > + PRU_TYPE_PRU = 0, > > + PRU_TYPE_RTU, > > + PRU_TYPE_TX_PRU, > > + PRU_TYPE_MAX, > > +}; > > + > > +/** > > + * struct pru_private_data - device data for a PRU core > > + * @type: type of the PRU core (PRU, RTU, Tx_PRU) > > + * @is_k3: flag used to identify the need for special load & event handling > > + */ > > +struct pru_private_data { > > + enum pru_type type; > > + unsigned int is_k3 : 1; > > +}; > > + > > /** > > * struct pru_rproc - PRU remoteproc structure > > * @id: id of the PRU core within the PRUSS > > * @dev: PRU core device pointer > > * @pruss: back-reference to parent PRUSS structure > > * @rproc: remoteproc pointer for this PRU core > > + * @data: PRU core specific data > > * @mem_regions: data for each of the PRU memory regions > > * @fw_name: name of firmware image used during loading > > * @mapped_irq: virtual interrupt numbers of created fw specific mapping > > @@ -93,6 +123,7 @@ struct pru_rproc { > > struct device *dev; > > struct pruss *pruss; > > struct rproc *rproc; > > + const struct pru_private_data *data; > > struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; > > const char *fw_name; > > int *mapped_irq; > > @@ -318,11 +349,12 @@ static int pru_rproc_start(struct rproc *rproc) > > { > > struct device *dev = &rproc->dev; > > struct pru_rproc *pru = rproc->priv; > > + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; > > u32 val; > > int ret; > > > > - dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n", > > - pru->id, (rproc->bootaddr >> 2)); > > + dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n", > > + names[pru->data->type], pru->id, (rproc->bootaddr >> 2)); > > > > ret = pru_handle_intrmap(rproc); > > /* > > @@ -344,9 +376,10 @@ static int pru_rproc_stop(struct rproc *rproc) > > { > > struct device *dev = &rproc->dev; > > struct pru_rproc *pru = rproc->priv; > > + const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" }; > > u32 val; > > > > - dev_dbg(dev, "stopping PRU%d\n", pru->id); > > + dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id); > > > > val = pru_control_read_reg(pru, PRU_CTRL_CTRL); > > val &= ~CTRL_CTRL_EN; > > @@ -458,9 +491,53 @@ static struct rproc_ops pru_rproc_ops = { > > .da_to_va = pru_rproc_da_to_va, > > }; > > > > +/* > > + * Custom memory copy implementation for ICSSG PRU/RTU Cores > > Please update this to add Tx_PRU as well to the list here and in the below > description. Sure. > > > + * > > + * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that > > + * is not seen on previous generation SoCs. The data is reflected properly in > > + * the IRAM memories only for integer (4-byte) copies. Any unaligned copies > > + * result in all the other pre-existing bytes zeroed out within that 4-byte > > + * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the > > + * IRAM memory port interface does not allow any 8-byte copies (as commonly > > + * used by ARM64 memcpy implementation) and throws an exception. The DRAM > > + * memory ports do not show this behavior. Use this custom copying function > > + * to properly load the PRU/RTU firmware images on all memories for simplicity. > > This last line is obsolete now that we use regular memcpy for Data RAM copies. Yes you are right. I will remove the last sentence. Thank you, Grzegorz