From: Anand Moon <linux.amoon@gmail.com>
To: Dragan Simic <dsimic@manjaro.org>
Cc: Hugh Cole-Baker <sigmaris@gmail.com>,
Jimmy Hon <honyuenkwun@gmail.com>,
Tianling Shen <cnsztl@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Grzegorz Sterniczuk <grzegorz@sternicz.uk>,
Jonas Karlman <jonas@kwiboo.se>,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: rockchip: fix eMMC corruption on NanoPC-T6 with A3A444 chips
Date: Mon, 20 Oct 2025 08:43:18 +0530 [thread overview]
Message-ID: <CANAwSgRuPhgnGy=2oY6u1jQtDRkQAdPqGv5NUNv8+WDeHq-56Q@mail.gmail.com> (raw)
In-Reply-To: <047fe2b8-0f94-0f0f-5964-b65844834706@manjaro.org>
Hi Dragan,
On Sun, 19 Oct 2025 at 23:40, Dragan Simic <dsimic@manjaro.org> wrote:
>
> Hello Anand,
>
> On Sunday, October 19, 2025 19:25 CEST, Anand Moon <linux.amoon@gmail.com> wrote:
> > Would you consider the following patch?
> >
> > As per the Rockchip RK3588S SoC Technical Reference Manual (TRM) Part 1,
> > chapter 21.6, Interface Description, the eMMC signals require careful handling
> > to ensure signal integrity.
> >
> > I2C2_SCL_M2 I/O EMMC_RSTN/I2C2_SCL_M2/UART5_RTSN_M1/GPIO2_A3_d
> > BUS_IOC_GPIO2A_IOMUX_SEL_L[15:12]=0x9
> > I2C2_SDA_M2 I/O EMMC_DATA_STROBE/I2C2_SDA_M2/UART5_CTSN_M1/GPIO2_A2_d
> > BUS_IOC_GPIO2A_IOMUX_SEL_L[11:8]=0x9
> >
> > $ git diff .
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
> > b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
> > index 6584d73660f6..f60a1d8be0ef 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
> > @@ -327,7 +327,7 @@ emmc {
> > emmc_rstnout: emmc-rstnout {
> > rockchip,pins =
> > /* emmc_rstn */
> > - <2 RK_PA3 1 &pcfg_pull_none>;
> > + <2 RK_PA3 1 &pcfg_pull_down_drv_level_2>;
> > };
> >
> > /omit-if-no-ref/
> > @@ -369,7 +369,7 @@ emmc_cmd: emmc-cmd {
> > emmc_data_strobe: emmc-data-strobe {
> > rockchip,pins =
> > /* emmc_data_strobe */
> > - <2 RK_PA2 1 &pcfg_pull_down>;
> > + <2 RK_PA2 1 &pcfg_pull_down_drv_level_2>;
> > };
> > };
>
> Frankly, I'm not really sure how would such changes do something
> good regarding the eMMC signal integrity? In general, signal
> integrity depends mostly on the routing of the PCB traces, which
> is purely hardware design. Sure, termination of data lines also
> plays a significant role, but that surely isn't at play here.
>
It is necessary to enhance the signal quality from the controller to
the eMMC module
> Moreover, the eMMC RSTn line is already pulled high to VCCIO in
> the reference RK3588 design, so pulling it down in the SoC itself
> would be pretty much wrong thing to do.
>
It is specified in the TRM that this is only applicable during
initialization.as per my understanding.
Thanks
-Anand
next prev parent reply other threads:[~2025-10-20 3:13 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 7:39 [PATCH] arm64: dts: rockchip: fix eMMC corruption on NanoPC-T6 with A3A444 chips Tianling Shen
2025-10-17 10:25 ` Dragan Simic
2025-10-17 12:08 ` Tianling Shen
2025-10-17 15:15 ` Dragan Simic
2025-10-17 16:34 ` Tianling Shen
2025-10-17 16:51 ` Dragan Simic
2025-10-18 0:42 ` Jimmy Hon
2025-10-18 8:30 ` Dragan Simic
2025-10-18 12:14 ` Hugh Cole-Baker
2025-10-18 13:57 ` Dragan Simic
2025-10-19 17:25 ` Anand Moon
2025-10-19 18:09 ` Dragan Simic
2025-10-20 3:13 ` Anand Moon [this message]
[not found] ` <CABGV7H_pTkJ_-WQNgVbGE+Ys7jOZaKcRrnMtPr8idfKoYMgKjg@mail.gmail.com>
2025-10-19 17:04 ` Dragan Simic
2025-10-20 1:53 ` Shawn Lin
2025-10-20 4:44 ` Tianling Shen
2025-10-20 8:20 ` Shawn Lin
2025-10-27 17:34 ` Tianling Shen
2025-10-30 9:16 ` Jianfeng Liu
2025-11-01 11:54 ` Heiko Stuebner
2025-11-01 12:14 ` Tianling Shen
2025-11-01 12:50 ` Dragan Simic
2025-11-05 11:59 ` Anand Moon
-- strict thread matches above, loose matches on Subject: below --
2025-10-20 9:41 Dragan Simic
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