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Sat, 03 May 2025 14:01:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMPD8yryO4aAzVK3k9gU+rNogRSOlsGH1wBDwPmv/JPT86SoET3Mma8EmUZRb50amWkhM6oJtI4sBpmUEyplY= X-Received: by 2002:a17:90b:5247:b0:30a:204e:fe47 with SMTP id 98e67ed59e1d1-30a4e238283mr11780230a91.16.1746306113484; Sat, 03 May 2025 14:01:53 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> <20250424-sm8750-display-dts-v1-1-6fb22ca95f38@linaro.org> <81205948-ae43-44ee-aa07-e490ea3bba23@oss.qualcomm.com> <97ae84c6-0807-4b19-a474-ba76cc049da9@quicinc.com> <858be1b7-0183-47b3-97b5-7d162b5748d3@quicinc.com> In-Reply-To: <858be1b7-0183-47b3-97b5-7d162b5748d3@quicinc.com> From: Dmitry Baryshkov Date: Sun, 4 May 2025 00:01:45 +0300 X-Gm-Features: ATxdqUH-zEu-Q8hx-hTs8Z0lWJcS4Lo1m6nzdFEbyO0oOCxxmfUEzj_5GmMtR44 Message-ID: Subject: Re: [PATCH RFC/WIP 1/4] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC To: Abhinav Kumar Cc: Konrad Dybcio , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jessica Zhang , Abhinav Kumar , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAzMDE5NCBTYWx0ZWRfXzEbu+kpMVlYg //oaInTQYcEzI7Odu9O1TeVT4zYUBqsIzwSXyB8gGLOeLfvxRvkgySZINAmeHWoRA1f4+PpbUhQ yZwJkD5ot3OLyJffacofuPzub0oYDWlvcpiw7UKheqNA3CThDH5gGaoXXk6fvC7GBS4zUU1Qs9a xAzxLlGEE0jEcfAVrZb+0UGahuamQHSMWtG9Vru1Khn3Plcx2/lBIwUJXtG9hVmYHvla0Ywt3FI xegmiLUdjbAvMpAJr2iSWhcCbEA30GqnLDfBCySzbObpsC85XyHy3Ah2FbuHO1FekP0/UUTkgSS Vd2N5F3LyB5GoZCF1UYF4iI0C2dYE8NnpOOqgo+4lNuU6Xe//70JJuSNqH3VY+FZQjmP8GbnLdd ZQ9vqeBkD3XIZqqoMaYxus9D0KcOHJwjVvmwZwuy3ZqyGYJ4/D1YkE0pabpAV6kGFLOPblgS X-Authority-Analysis: v=2.4 cv=M9RNKzws c=1 sm=1 tr=0 ts=68168443 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=E0QJNo61N1AVLolVTSsA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: mhr3ir-k3rWXc04yhmrwBnWsZAWEaqUO X-Proofpoint-ORIG-GUID: mhr3ir-k3rWXc04yhmrwBnWsZAWEaqUO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-03_09,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505030194 On Sat, 3 May 2025 at 22:59, Abhinav Kumar wrote: > > > > On 5/2/2025 10:51 PM, Dmitry Baryshkov wrote: > > On Tue, Apr 29, 2025 at 04:07:24PM -0700, Abhinav Kumar wrote: > >> > >> > >> On 4/28/2025 2:31 PM, Konrad Dybcio wrote: > >>> On 4/24/25 3:04 PM, Krzysztof Kozlowski wrote: > >>>> Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, > >>>> DisplayPort and Display Clock Controller. > >>>> > >>>> Signed-off-by: Krzysztof Kozlowski > >>>> > >>>> --- > >>> > >>> [...] > >>> > >>>> + mdp_opp_table: opp-table { > >>>> + compatible = "operating-points-v2"; > >>>> + > >>> > >>> The computer tells me there's also a 156 MHz rate @ SVS_D1 > >>> > >>> Maybe Abhinav could chime in whether we should add it or not > >>> > >> > >> Yes I also see a 156Mhz for LOW_SVS_D1 but we had a similar entry even for > >> sm8650 and did not publish it in the dt. > >> > >> It was present till sm8450.dtsi but dropped in sm8550/sm8650 even though > >> LOW_SVS_D1 is present even on those. > >> > >> I think the reason could be that the displays being used on the reference > >> boards will need a pixel clock of atleast >= low_svs and the MDP clock > >> usually depends on the value of the DSI pixel clock (which has a fixed > >> relationship to the byte clock) to maintain the data rate. So as a result > >> perhaps even if we add it, for most displays this level will be unused. > >> > >> If we end up using displays which are so small that the pixel clock > >> requirement will be even lower than low_svs, we can add those. > >> > >> OR as an alternative, we can leave this patch as it is and add the > >> low_svs_d1 for all chipsets which support it together in another series that > >> way it will have the full context of why we are adding it otherwise it will > >> look odd again of why sm8550/sm8650 was left out but added in sm8750. > > > > I think it's better to describe hardware accurately, even if the > > particular entry ends up being unused. I'd vote for this option. > > > >>> [...] > >>> > >>>> + mdss_dsi_opp_table: opp-table { > >>>> + compatible = "operating-points-v2"; > >>>> + > >>> > >>> Similarly there's a 140.63 MHz rate at SVS_D1, but it seems odd > >>> with the decimals > >> > >> For this one, yes its true that LOW_SVS_D1 is 140.63Mhz for sm8750 but this > >> voltage corner was somehow never used for DSI byte clock again I am thinking > >> this is because for the display resolutions we use, we will always be >= > >> low_svs so the low_svs_d1 will never hit even if we add it. > > > > Please add all voltage/frequency corners. Think about low-res DP or > > low-res, low-rate WB. > > > > Sounds good, lets go ahead and add all the voltage/freq corners. > > Like I noted, even for sm8550/sm8650 the low_svs_d1 was missed out, so > if we are adding it for sm8750 now in this series, a follow up patch > should also be sent to add them for sm8550/sm8650 as well. That way we > will fix them all up together and this does not come across as a > discrepancy. Abhinav, if you know a missing piece, please send a patch, fixing it. -- With best wishes Dmitry