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From: hammer hsieh <hammerh0314@gmail.com>
To: Greg KH <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jirislaby@kernel.org>,
	robh+dt@kernel.org, linux-serial@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	p.zabel@pengutronix.de, wells.lu@sunplus.com,
	"hammer.hsieh" <hammer.hsieh@sunplus.com>
Subject: Re: [PATCH v6 2/2] serial:sunplus-uart:Add Sunplus SoC UART Driver
Date: Fri, 28 Jan 2022 11:36:10 +0800	[thread overview]
Message-ID: <CAOX-t54bRS0_kgg2DVoF3p8fx9VJh7xbyoTFcnAHnimLv40WbQ@mail.gmail.com> (raw)
In-Reply-To: <YfFQ7v4dXPMV7ypw@kroah.com>

Hi, Greg KH:

I review all driver again.
I think only startup and shutdown not good.
I will modify like below.
If you are ok, I will submit next patch.

static int sunplus_startup(struct uart_port *port)
{
        unsigned long flags;
        unsigned int isc;
        int ret;

        ret = request_irq(port->irq, sunplus_uart_irq, 0, "sunplus_uart", port);
        if (ret)
                return ret;

        spin_lock_irqsave(&port->lock, flags);

        isc = readl(port->membase + SUP_UART_ISC); //add this line
        isc |= SUP_UART_ISC_RXM;
        writel(isc, port->membase + SUP_UART_ISC);

        spin_unlock_irqrestore(&port->lock, flags);

        return 0;
}

static void sunplus_shutdown(struct uart_port *port)
{
        unsigned long flags;
        unsigned int isc;

        spin_lock_irqsave(&port->lock, flags);

        isc = readl(port->membase + SUP_UART_ISC); //add this line
        isc &= ~(SUP_UART_ISC_RXM | SUP_UART_ISC_TXM); //add this line
        writel(isc, port->membase + SUP_UART_ISC); //modify this line

        spin_unlock_irqrestore(&port->lock, flags);

        free_irq(port->irq, port);
}

Greg KH <gregkh@linuxfoundation.org> 於 2022年1月26日 週三 下午9:47寫道:
>
> On Fri, Jan 14, 2022 at 10:22:56AM +0800, hammer hsieh wrote:
> > Jiri Slaby <jirislaby@kernel.org> 於 2022年1月13日 週四 下午7:12寫道:
> > >
> > > On 13. 01. 22, 11:56, hammer hsieh wrote:
> > > >> Could you explain me what posted write is and how does it not matter in
> > > >> this case?
> > > >>
> > > >
> > > > Each UART ISC register contains
> > >
> > > No, you still don't follow what I write. Use your favorite web search
> > > for "posted write" and/or consult with your HW team.
> > >
> >
> > Maybe this time, we are on the same page.
> > Our SP7021 chipset is designed on ARM Cortex-A7 Quad core.
> > Register Access through AMBA(AXI bus), and it is non-cached.
> >
> > Did you mean
> > case1 have concern about "posted write", and you want to know why it not matter?
> > case2 will be safer?
> >
> > Case1 :
> > spin_lock_irq_save()
> > writel(0, target register)
> > spin_unlock_irqrestore()
>
> A lock does not mean that your write made it to the device.  Please talk
> to the hardware designers to properly determine how to correctly write
> to the hardware and "know" that the write succeeded or not.  This driver
> does not seem to take that into consideration at all.
>
> thanks,
>
> greg k-h

      reply	other threads:[~2022-01-28  3:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-12  9:24 [PATCH v6 0/2] Add UART driver for Suplus SP7021 SoC Hammer Hsieh
2022-01-12  9:24 ` [PATCH v6 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver Hammer Hsieh
2022-01-12  9:24 ` [PATCH v6 2/2] serial:sunplus-uart:Add " Hammer Hsieh
2022-01-13  7:06   ` Jiri Slaby
2022-01-13  8:54     ` hammer hsieh
2022-01-13  9:08       ` Jiri Slaby
2022-01-13 10:56         ` hammer hsieh
2022-01-13 11:12           ` Jiri Slaby
2022-01-14  2:22             ` hammer hsieh
2022-01-26 13:47               ` Greg KH
2022-01-28  3:36                 ` hammer hsieh [this message]

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